NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 67

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

Electrical, Mechanical, and Thermal Specification
VCC_USB, VCC_IO, VCC_MEM,
VCC_BB, VCC_LCD, VCC_USIM
Figure 6-2. Power On Reset Timing
Table 6-2. Power-On Timing Specifications (Sheet 1 of 2)(OSCC[CRI] = 0)
Note: nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor will not
VCC_CORE, VCC_SRAM,
nBATT_FAULT
nVDD_FAULT
nRESET_OUT
VCC_BATT
VCC_PLL
PW R_EN
nRESET
SYS_EN
begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and
PWR_DEL timers have expired. Refer to the Intel® PXA27x Processor Family Developer’s
Manual, “Initial Power On” and “Deep-Sleep Exit States” for a state diagram.
Symbol
t
t
t
t
t
t
5. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE,
6. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system
7. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset
1
2
3
4
5
bramp
VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be
established within 125 milliseconds of the assertion of PWR_EN.
power supplies have been properly established.
vector.
t
bramp
Description
Delay from VCC_BATT assertion to
nRESET de-assertion
Delay from nRESET de-assertion to
SYS_EN assertion
Delay from SYS_EN assertion to
PWR_EN assertion
Power supply stabilization time (time to
the deassertion of nVDD_FAULT after the
assertion of PWR_EN)
Delay from the assertion of PWR_EN to
the de-assertion of nRESET_OUT
VCC_BATT power-on Ramp Rate
t
1
t
sysramp
t
2
t
3
Min
10
—
—
—
—
—
t
4
t
pwrramp
AC Timing Specifications
Typical
Intel® PXA270 Processor
10
125
125
10
—
—
1
t
5
Max
120
12
—
—
—
—
mV/uS
Units
ms
ms
ms
ms
ms
6-3