NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 69

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

6.2.3
6.2.4
Electrical, Mechanical, and Thermal Specification
Table 6-4. Hardware Reset Timing Specifications (OSCC[CRI] = 1)
Figure 6-4. GPIO Reset Timing
Note: When bit GPROD is set in the Power Manager General Configuration register, nRESET_OUT is
Watchdog Reset Timing
Watchdog reset is generated internally and therefore has no external pin dependencies. The
nRESET_OUT pin is the only indicator of watchdog reset; it stays asserted for t
timing is similar to that for GPIO reset — see
GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies
based on the selected clock frequency. If the clocks and power manager is in a frequency-change
sequence when GPIO reset is asserted (see
on page
timing specifications.
not asserted during GPIO reset. For register details, see the “Clocks and Power Manager” chapter
in the Intel® PXA27x Processor Family Developer’s Manual.
Symbol
t
t
t
6
7
8
GP[1]
nRESET_OUT
5-9.), then
nCS0
tDHW_OUT_A
Description
Delay between nRESET asserted and
nRESET_OUT asserted
Assertion time of nRESET
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
Figure 6-4
tA_GPIO<1>
shows the timing of GPIO reset, and
tDHW_OUT
Section 5.5.1, “32.768-kHz Oscillator Specifications”
Figure 6-4
for details.
2256
Min
—
tCS0
6
Table 6-5
AC Timing Specifications
Intel® PXA270 Processor
< 100 ns
Typical
—
—
shows the GPIO reset
DHW_OUT
3265
Max
10
—
. The
Units
ms
ms
ms
6-5