NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 82

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

Intel® PXA270 Processor
AC Timing Specifications
6.4.3
6-18
tromAS
tromCES
tromCEH
tromDSOH
SDCKE<1>
MA<24:10>
SDCLK<1>
SDCLK<2>
nSDCS<0>
nSDCS<2>
DQM<3:0>
Symbols
Figure 6-10. SDRAM Fly-by DMA Timing
MD<31:0>
Table 6-16. ROM AC Specification (Sheet 1 of 2)
command
DVAL<0>
DVAL<1>
nSDRAS
nSDCAS
RDnWR
Note:
nWE
NOTES:
DVAL<0> is asserted.
Latch data on rising edge of SDCLK<1> when
ROM Parameters and Timing Diagrams
Table 6-16
Figure 6-14
Table 6-16
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Address setup to nCS assert
nCS setup to nOE asserted
nCS hold from nOE deasserted
MD setup to address valid
read
col
1. MDCNFG[DTC] = 0b00 (CL = 2, tRP = 2 clk, tRCD = 1 clk)
2. See the SDRAM timing diagram.
bank
pre
lists the timings for ROM reads. See
lists programmable register items. See the “Memory Controller” chapter in the Intel®
for timings diagrams representing burst and non-burst ROM reads.
Parameters
nop
rd0
0b0000
latch data rd0
row
act
rd1
latch data rd1
rd2
latch data rd2
rd3
latch data rd3
MIN
nop
1.5
—
—
1
Electrical, Mechanical, and Thermal Specification
Using DVAL<1> driven two clocks early,
drive data on rising edge of SDCLK<2>.
Figure
latch DVAL[1] asserted
6-11,
TYP
—
—
—
—
mask0 mask1 mask2 mask3
drive data wd0
write
mask data bytes
wd0
col
Figure
drive data wd1
wd1
6-12,
MAX
—
1
0
0
drive data wd2
wd2
Figure
drive data wd3
nop
wd3
clk_mem
clk_mem
clk_mem
clk_mem
Units
6-13, and
†
Notes
—
—
—
—