MPC2F35E2 MEGAWIN [Megawin Technology Co., Ltd], MPC2F35E2 Datasheet - Page 9

• Manufacturer Part Number: MPC2F35E2
• Description: Low-speed USB micro-controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

Interrupt Registers
IRQ enable flag
Program can enable (setting to “1”) or disable (clearing to “0”) the ability of triggering IRQ through this
register.
IRQ status flag
When IRQ occurs, program can read this register to know which source triggering IRQ.
IRQ clear flag
Program can clear the interrupt event by writing ‘1’ into the corresponding bit.
Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit
from unknown errors. If the WDT overflows, the WDT reset function will be performed. RSTS (Bit 7 of
WDT_ST) is set by hardware when the WDT
writing 1 to bit 7 of WDT_CLR. The interval of WDT to cause reset is around 0.7s at 6MHz external
oscillator. Programming one into the bit 7 of WDT_CLR register can reset the contents of the WDT. In
normal operation, the application program must reset WDT before it overflows. A WDT overflow
indicates that operation is not under control and the chip will be reset. The organization of the watchdog
timer is shown as below
MEGAWIN
Address
Address
Address
Address
00DEH
00C1H
00C2H
00C3H
00DFH
USB: USB finishes Rx or Tx data
TM0: Timer0 underflow
P3: Falling edge trigger signal occurs at port 3 input mode
INT0, INT1: Falling edge trigger signal occurs at P0.4 and P0.5 input mode
Bit 3 ~ Bit 0: Contents of WDT
RSTS: WDT reset status, set by the hardware when WDT overflows, and clear by the firmware or
CLR: RSTS clear and WDT reset control bit, the program can clear the RSTS bit and reset WDT
the hardware reset
by writing “1” into the CLR bit
WDT_CLR
IRQ_CLR
WDT_ST
IRQ_EN
IRQ_ST
Name
Name
Name
Name
RSTS
Bit 7
Bit 7
Bit 7
Bit 7
CLR
-
-
-
MPC2F35_USB Data Sheet
Bit 6
Bit 6
Bit 6
Bit 6
-
-
-
-
-
INT1
INT1
INT1
Bit 5
Bit 5
Bit 5
Bit 5
-
-
overflows.
counter,
INT0
INT0
INT0
Bit 4
Bit 4
Bit 4
Bit 4
-
-
It also can be cleared by hardware reset or
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
which is designed to prevent the program
P3
P3
P3
-
Bit 2
TM0
Bit 2
TM0
Bit 2
TM0
Bit 2
Bit 2
-
Bit 1
USB
Bit 1
USB
Bit 1
USB
Bit 1
Bit 1
-
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
-
-
-
-
R
R
R
R
√
√
√
-
-
9
W
W
W
W
√
√
√
-
-