MPC2F35E2 MEGAWIN [Megawin Technology Co., Ltd], MPC2F35E2 Datasheet
MPC2F35E2
Related parts for MPC2F35E2
MPC2F35E2 Summary of contents
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... Support two power-saving modes: stop and halt mode • Packages: − 28-SSOP: MPC2F35L − 40-PDIP: MPC2F35E2 This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue this product without notice. © MEGAWIN Technology Co., Ltd. 2008 All rights reserved. Low-speed USB micro-controller MEGAWIN ...
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PAD DESCRIPTION PIN Name I/O P0.0~0.3 I/O P0.4/- INT0 I/O P0.5/- INT1 I/O P0.6~0.7 I/O P1.0~1.7 I/O P2.0~2.7 I/O P3.0~3.7 I/O P4.0~4.1 I/O - RST I XTAL1 I XTAL2 I D+/SCLK I/O D-/SDATA I ...
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BLOCK DIAGRAM 256 bytes RAM 8K bytes Flash ROM 8-bit Timer Power Controller 8-bit CPU Interrupt Power-on Controller Reset MEGAWIN I/O PORTs DPM Control Acess Control USB and PS/2 Engine Watch Dog Timer MPC2F35_USB Data Sheet Port 0.0 ~ 0.7 ...
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... RST P0 P3.7 8 P0.7 21 P3.4 P1.4 9 P3 P2.7 11 P1.7 18 P2.6 P2.0 12 P2 P2.4 14 P2.2 15 P2.3 MPC2F35L 1 Vcc 40 V3.3 2 P0.3/LED3 39 3 P0.2/LED2 38 4 Vss P0.1/LED1 37 Xtal1 5 P0.0/LED0 36 Xtal2 6 - RST P3.6 33 P0.6 9 P3.5 32 P0.7 P3 P1.0 P3 P1.1 12 P3.2 29 P1.2 13 P3.1 28 P1.3 P3 P1.4 15 P2.7 26 P1.5 P2 P1.6 P2 P1.7 P2 P2.0 P2 P2.1 P2 MPC2F35E2 MPC2F35_USB Data Sheet MEGAWIN ...
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FUNCTION DESCRIPTION Registers PCH PCL 1 S Accumulator The accumulator is a 8-bit register, which stores the results of most arithmetic and logic operations. In addition, the accumulator usually contains one of two data words used ...
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Stack Pointer (S) The stack pointer is an 8-bit register, which is used to control the addressing of the variable-length stack. The stack pointer is automatically incremented and decremented under the control of the MCU to perform the stack manipulations. ...
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Special Function Register (SFR) The address 00C0H to 00FFH and 0200H to 027FH are reserved for the special function registers (SFR). MPC2F35 has 36 SFRs to be used to control or store the status of I/O, timers, system clock and ...
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Interrupt Vectors Vector Address Item 8002H, 8003H RESET 8006H, 8007H USB 8008H, 8009H TM0 800AH, 800BH P3 800CH, 800DH INT0 800EH, 800FH INT1 There are six interrupt sources provided in MPC2F35. The flag IRQ_EN and IRQ_ST are used to control ...
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Interrupt Registers IRQ enable flag Address Name Bit 7 00C1H IRQ_EN - Program can enable (setting to “1”) or disable (clearing to “0”) the ability of triggering IRQ through this register. USB: USB finishes data TM0: Timer0 ...
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Fosc/2^18 System Control Registers Power saving control Address Name Bit 7 0200H PWR_CTL LVDT LVDT: Low-voltage detector disable bit. 1: Disable, 0: Enable (default) CKC: Oscillator control bit. 1: Disable OSC, 0: Enable OSC (default) HALT: FCPU off-line control bit. ...
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FCPU_SR - At the 6M Hz external crystal, the internal clock source of MPC2F35 the default value. CKS: F clock source select register. 0: FOSC/2 (default), 1:FOSC CPU Release halt mode enable flag Address Name ...
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TM0 F Frequency TM0_UV 00H Invalid 01H 93.75 KHz 02H 62.5 KHz … … FFH 732.42 Hz General Purpose I/O Ports Port 0 Address Name Bit 7 00D0H P0_BUF BP07 00D8H P0 P07 0240H P0_CR CP07 0241H P0_MR - Port ...
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Address Name Bit 7 00D1H P1_BUF BP17 00D9H P1 P17 0244H P1_CR CP17 0245H P1_MR - Port 8-bit I/O port. Its structure is the same with Port P1_BUF: Port 1 output buffer. When P1.n is configured as ...
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P3_CR: Configure P3 input or output individually. 0: input, 1: output P3_MR: Configure the output mode of P3.0 ~ P3.7 with a 17k ohm pull-high resistor, CMOS or NMOS open drain When port 3 is used ...
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USB INTERFACE MPC2F35 provides the interface of PS/2 and USB combinative operation by programming the below registers, the user can be easily change the configuration between USB and PS/2 for meeting the environment of the host. USB register access control ...
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Write 0 into the URD bit 4. Whenever USB engine finished a transaction, it will generate an interrupt to acknowledge MPC2F35. The user can get information about the transaction through the above sequence. When USB engine received a reset instruction ...
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USB Special Function Registers (SFRs) Summary There are 18 special function registers for the operation of Universal Serial Bus (USB). The detail definition is described as the following: Mnemonic USB Device SFRs DCON Device Control Register FADDR Function Address Register ...
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USB SFR Description DCON: Device Control Register Read/Write Default: 0XXX_XX00 Bit Bit Number Mnemonic 7 TEST mode Enable: TESTEN Use for test only. In normal operation, this bit should be cleared to “0”. 6 Reserved: - Write zero to this ...
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FADDR: USB Function Address Register Read/Write Default: X000_0000 Bit Bit Number Mnemonic 7 Reserved: - Write zero to this bit. 6:0 Function Address: A [6:0] This register holds the address for the USB function. During bus enumeration written ...
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FPCON: Function Power Control Register Read/Write Default: XX0X_xX00 Bit Bit Number Mnemonic 7 - Reserved: Write zero to this bit Reserved: Write zero to this bit. 5 FRWU Function Remote Wake-up Trigger: This bit is used by the ...
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FIE: Function Interrupt Enable Register Read/Write Default: XXX0_0000 Bit Bit Number Mnemonic 7 - Reserved: Write zero to this bit Reserved: Write zero to this bit Reserved: Write zero to this bit. 4 FRXIE3 Function Receive ...
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FIFLG: Function Interrupt Flag Register Read/Write Default: XXX0_0000 Bit Bit Number Mnemonic 7 - Reserved: Write zero to this bit Reserved: Write zero to this bit Reserved: Write zero to this bit. 4 FRXD3 Function Receive ...
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IEN1: USB Interrupt Enable Register Read/Write Default: XXXX_0X0X Bit Bit Number Mnemonic 7 - Reserved: Write “one” to this bit Reserved: Write zero to this bit Reserved: Write zero to this bit Reserved: Write ...
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EPINDEX: Endpoint Index Register Read/Write Default: XXXX_XX00 Bit Bit Number Mnemonic 7 Reserved: - Write zero to this bit. 6 Reserved: - Write zero to this bit. 5 Reserved: - Write zero to this bit Reserved: Write zero ...
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EPCON: Endpoint Control Register (Endpoint-Indexed) Read/Write Default: 00XX_X0X0 Bit Bit Number Mnemonic 7 Stall Receive Endpoint: RXSTL Set this bit to stall the receive endpoint. 6 Stall Transmit Endpoint: TXSTL Set this bit to stall the transmit endpoint ...
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RXCNT: Receive FIFO Byte-Count Register (Endpoint-Indexed) Read Only Default: XXXX_0000 Bit Bit Number Mnemonic 7 Reserved: - Write zero to this bit. 6 Reserved: - Write zero to this bit. 5 Reserved: - Write zero to this bit. 4 Reserved: ...
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RXCON: Receive FIFO Control Register (Endpoint-Indexed) Read/Write Default: 0XX0_XXXX Bit Bit Number Mnemonic 7 Receive FIFO Clear: RXCLR Set this bit to flush the entire receive FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit ...
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RXDAT: Receive FIFO Data Register (Endpoint-Indexed) Read Only Default: XXXX_XXXX Bit Bit Number Mnemonic 7:0 Receive FIFO data specified by EPINDEX is stored and read from this RD [7:0] register. 28 Function MPC2F35_USB Data Sheet Address: 23H System Reset or ...
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RXSTAT: Endpoint Receive Status Register (Endpoint-Indexed) Read/Write Default: 0000_0XXX Bit Bit Number Mnemonic 7 Receive Endpoint Sequence Bit (read, conditional write): RXSEQ The bit will be toggled on completion of an ACK handshake in response to an OUT token. This ...
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TXCNT: Transmit FIFO Byte-Count Register (Endpoint-Indexed) Write Only Default: XXXX_XXXX Bit Bit Number Mnemonic 7 Reserved: - Write zero to this bit. 6 Reserved: - Write zero to this bit. 5 Reserved: - Write zero to this bit. 4 Reserved: ...
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TXCON: Transmit FIFO Control Register (Endpoint-Indexed) Read/Write Default: 0XXX_XXXX Bit Bit Number Mnemonic 7 Transmit FIFO Clear: TXCLR Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware clears this bit ...
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TXDAT: Transmit FIFO Data Register (Endpoint-Indexed) Write Only Default: XXXX_XXXX Bit Bit Number Mnemonic 7:0 Data to be transmitted in the FIFO specified by EPINDEX is written to this TD [7:0] register. 32 Function MPC2F35_USB Data Sheet Address: 33H System ...
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TXSTAT: Endpoint Transmit Status Register (Endpoint-Indexed) Read/Write Default: 0XXX_0XXX Bit Bit Number Mnemonic 7 Transmit Endpoint Sequence Bit (read, conditional write): TXSEQ The bit will be transmitted in the next PID and toggled on a valid ACK handshake of an ...
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... P0.4/-INT0 8 P0.5/-INT1 P1.4 16 C14 P1.5 17 C13 P1.6 18 C12 P1.7 19 C11 P2.0 20 C15 P2.1 MPC2F35E2_40 pin DIP MPC2F35_USB Data Sheet 10 uF 0 VCC C5 C6 10u 0.1u 40 Vcc 39 P0.3/LED3 ScrollLock 38 P0.2/LED2 D1 CapsLock 37 P0.1/LED1 D2 36 P0.0/LED0 D3 35 /RST P3.5 ...
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Absolute Maximum Rating PARAMETER Supply Voltage to Ground Potential Maximum current per pin excluding V Maximum current out of GND Maximum current out of VCC Ambient Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum ...
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PACKAGE DIMENSIONS 40-pin DIP 28-SSOP 36 MPC2F35_USB Data Sheet MEGAWIN ...
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Instruction Set Summary Symbol Description ACC: Accumulator (ACC): Contents of Accumulator ACC.n: Accumulator bit n X: Index Register X Y: Index Register Y SP: Stack Pointer Register PC: Program Counter #data: Constant parameter C: Carry Flag Z: Zero Flag I: ...
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Instruction Set Summary (212 instructions) Mnemonic Operand(s) ADC addr 8 #data (addr 8) addr , X 8 (addr , X) 8 (addr ), Y 8 addr 16 addr , X 16 addr , Y 16 SBC addr 8 #data (addr ...
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Mnemonic Operand(s) ORA addr 8 #data (addr 8) addr , X 8 (addr , X) 8 (addr ), Y 8 addr 16 addr , X 16 addr , Y 16 EOR addr 8 #data (addr 8) addr , X 8 ...
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Mnemonic Operand(s) CLC CLI CLD CLV RMB0 addr 8 … RMB7 addr 8 SEC SEI SED SMB0 addr 8 … SMB7 addr 8 INC A INC addr 8 addr , X 8 addr 16 addr , X 16 INX INY ...
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Mnemonic Operand(s) ROL A ROL addr 8 addr , X 8 addr 16 addr , X 16 ROR A ROR addr 8 addr , X 8 addr 16 addr , X 16 ASL A ASL addr 8 addr , X ...
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Mnemonic Operand(s) LDA #data LDA addr 8 (addr 8) addr , X 8 (addr , X) 8 (addr ), Y 8 addr 16 addr , X 16 addr , Y 16 LDX #data addr 8 addr , Y 8 addr ...
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Mnemonic Operand(s) STA addr 8 (addr 8) addr , X 8 (addr , X) 8 (addr ), Y 8 addr 16 addr , X 16 addr , Y 16 STX addr 8 addr , Y 8 addr 16 STY addr ...
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Mnemonic Operand(s) JMP label (label ) (label BRA addr8 BEQ addr 8 (relative) BNE addr 8 BCS addr 8 BCC addr 8 BMI addr 8 BPL addr 8 BVS addr 8 BVC addr 8 BIT addr 8 addr ...
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Mnemonic Operand(s) JSR label RTS RTI PHA PHP PHX PHY PLA PLP PLX PLY NOP ** Note: Add one clock period if branch occurs to location in same page. Add two clock periods if branch to another page occurs. MEGAWIN ...
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Revision History VERSION DATE PAGE A1 2004/ 2005/01 A3 17~33 2005/07 A4 2008/12 46 DESCRIPTION Initial issue Application circuit has been modified. Revised USB Special Function Registers (SFRs) Summary and USB SFR Description. Formatting MPC2F35_USB Data Sheet MEGAWIN ...