MA007AD MEGAWIN [Megawin Technology Co., Ltd], MA007AD Datasheet
MA007AD
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MA007AD Summary of contents
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... MEGAWIN Technology Co., Ltd. 2006 All rights reserved. 3-in-1 8-bit serial to parallel latch • 5 MHz (typical) shift out frequency • Output capability: ♦ Parallel outputs; bus driver ♦ Serial output; standard MA007AP MA007AD 44-PLCC 48-LQFP 24 pins 20mA MA007A MA007AF 44-PQFP 2005/11 version A1 MEGAWIN ...
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General Description The MA007 are high-speed Si-gate CMOS devices. There are three groups 8-stage serial shift register with a storage register and 3-state outputs in MA007. The shift register and storage register have separate clocks. Data is shifted on the ...
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Block Diagram 4 SCLK 3 /SCLR 2 PCLK 1 /OE 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER 3-STATE OUTPUTS MEGAWIN 8-STAGE SHIFT REGISTER 8-BIT STORAGE REGISTER 3-STATE OUTPUTS MA007A Technical Summary 8-STAGE SHIFT REGISTER Dout0 10 Dout1 9 Dout2 8 8-BIT ...
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Function Description FUNCTION TABLE INPUTS SCLK PCLK /OE /SCLR D INx ↑ ↑ ↑ ↑ ↑ ...
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Application Circuit (Ext) VCC + C2 C3 470uF 0.1uF C U1 MLC031A/021A/017A_COB IC_VCC D6 D5 1N4148 R1 1N60P 680K C8 Li-Battery @4MHz 1 VDD 0.1uF 3.0V 2 OSCO 3 OSCI 4 GND 5 RES 6 TEST ...
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Pad Assignment PCLK /SCLR 3 SCLK 4 Din0 5 Din1 6 Din2 7 Dout2 8 Dout1 (0, ...
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Absolute Maximum Rating PARAMETER Supply Voltage to Ground Potential Applied Input / Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of ...
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AC Characteristics (VCC-GND = 5.0V 25° C; unless otherwise specified) PARAMETER Maximum clock pulse frequency (SCLK, PCLK) Propagation delay Setup Time Pulse Width Tri-state output enable time Tri-state output disable time Hold time Removal time 8 SYM. CONDITIONS ...
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System Timing SCLK to D Propagation Delay Waveforms OUTx SCLK D OUTx PCLK to Q Propagation Delay and Setup Time Waveforms Xn SCLK PCLK Q Xn MEGAWIN 1/F MAX 50 PHL1 T PLH1 1/F MAX T SU2 ...
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SCLK and PCLK are connected together to Q Waveforms SCLK PCLK Q Xn-1 PCLK to Q Propagation Delay and Setup Time Waveforms Xn /SCLR SCLK D INx D OUTx 10 Propagation Delay and Setup Time Xn-1 1/F MAX T SU3 ...
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Tri-state Enable/Disable Time Waveforms / Low-to-Off Off-to-Low Q Xn High-to-Off Off-to-High MEGAWIN T PZL T PLZ T T PHZ PZH Outputs Outputs Enable Disable MA007A Technical Summary Outputs Enable 11 ...
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Package Information MA007AE 48 Pin PDIP (600mil) Configuration 48 Pin PDIP Package Dimension 12 1 Din0 48 SCLK 2 47 /SCLR Din1 46 PCLK Din2 /OE Dout2 5 GND Dout1 44 43 VCC Dout0 6 GND 7 ...
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MA007AP 44 Pin PLCC Configuration GND VCC Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 GND 44 Pin PLCC Package Dimension MEGAWIN ...
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... MA007AD 48 Pin LQFP Configuration VCC Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 GND Q17 Q16 48 Pin LQFP Package Dimension MA007A Technical Summary VCC 36 GND 35 Q00 34 Q01 33 Q02 32 Q03 31 Q04 30 Q05 29 Q06 28 Q07 27 VCC 26 Q10 ...
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MA007AF 44 Pin PQFP Configuration GND /OE PCLK /SCLR SCLK Din0 Din1 Din2 Dout2 Dout1 Dout0 44 Pin PQFP Package Dimension MEGAWIN MA007A Technical Summary Q10 33 Q11 32 ...
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Notes: Vision History VERSION DATE PAGE A1 Nov. 2005 16 DESCRIPTION Initial issue. MA007A Technical Summary MEGAWIN ...