MG87FE/L2051 MEGAWIN [Megawin Technology Co., Ltd], MG87FE/L2051 Datasheet

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... Megawin Technology Co., Ltd. MG87FE/L2051/4051/6051 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D Data Sheet Ver 1.03 1/56 ...

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... UART Structure................................................................................................................... 30 11.2. UART Register.................................................................................................................... 31 12. Analog Comparator .................................................................................... 33 12.1. Analog Comparator Structure ............................................................................................. 33 12.2. Analog Comparator Register .............................................................................................. 34 13. Watch Dog Timer (WDT)............................................................................ 35 13.1. WDT Structure .................................................................................................................... 35 13.2. WDT Register ..................................................................................................................... 35 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG87FE/L2051/4051/6051 Content Preliminary, v 1.03 2/56 ...

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... Auxiliary SFRs............................................................................................ 46 20. Option Setting ............................................................................................ 48 21. Absolute Maximum Rating ......................................................................... 49 22. Electrical Characteristics............................................................................ 50 22.1. DC Characteristics .............................................................................................................. 50 23. Package Dimension ................................................................................... 51 24. Instruction Set ............................................................................................ 53 25. Revision History ......................................................................................... 56 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG87FE/L2051/4051/6051 Preliminary Ver 1.00 3/56 ...

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... In-System-Programming and In-Application-Programming allows the users to download new code or data while the microcontroller sits in one machine cycle in 6 clock cycles or 12 clock cycles. MG87FE/L2051/4051/6051 has one 8-bit I/O ports (P1), one 7-bit I/O port (P30~P35,P37), two 16-bit timer/counters, one PWM-timer -source, four-priority-level interrupt structure, an enhanced UART, a precision analog comparator, on-chip crystal oscillator(combined P42,P43) and a high-precision internal oscillator ...

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... MEGAWIN MAKE YOU WIN 2. Features 80C51 Central Processing Unit MG87FE/L2051 with 2KB flash ROM, 4051/4KB flash ROM; 6051/6KB flash ROM Operating voltage: E type: 4.5V~5.5V and L type: 2.4V~3.6V Operation frequency : 48MHz(max)@12T and 24MHz@6T mode - External crystal mode - Internal RC-oscillator with +/- 4% frequency drift @ -40 ~ 85℃, there are 6 kinds of frequencies ...

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... XTAL1/P4.3 XTAL OSC/ Port4 Driver XTAL2/P4.2 RST Logic RESET WDT This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG87FE/L2051/4051/6051 RAM256 PWM Timer Timer0/1 Int. OSC 8051 Core Interrupt Port1 Latch Port3 Latch + ...

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... MEGAWIN MAKE YOU WIN 4. Pin Configurations 4.1. Package Instruction This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG87FE/L2051/4051/6051 Preliminary Ver 1.00 7/56 ...

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... Crystal1: Input to the inverting oscillator amplifier. I/O XTAL1 has an alternate function for P4.3/INT2. P4.3/INT2 has a swapped function with P1.3. Crystal2: Output from the inverting amplifier. I/O XTAL2 has an alternate function for P42/INT3. P4.2/INT3 has a swapped function with P1.2. P POWER G GROUND MG87FE/L2051/4051/6051 Preliminary, v 1.03 Description 8/56 ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D RS1 RS0 SP[4] SP[3] SP[ DPL[4] DPL[3] DPL[ DPH[4] DPH[3] DPH[ B[4] B[3] B[2] MG87FE/L2051/4051/6051 Preliminary Ver 1. SP[1] SP[ DPL[1] DPL[ DPH[1] DPH[ B[1] B[0] 9/56 ...

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... MAKE YOU WIN 5.2. CPU Timing A machine cycle is the shortest timing period to achieve an instruction. In MG87FE/L2051/4051/6051, some instructions need 1 machine cycle to achieve, but others need machine cycles. A machine cycle takes 12 clock periods or 6 clock periods. For 12MHz system clock 1us or 0.5us. ...

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... Program memory in MG87FE/L2051/4051/6051 can only be read, not written into. 6.1. On-Chip Program Flash In MG87FE/L2051/4051/6051, the first partition named AP-memory is the space for storing user’s application program code. The second one named as IAP-memory and the space which is accessed by CPU for storing the user data ...

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... Bank0 00H MG87FE/L2051/4051/6051 has internal data RAM that is mapped into three separate segments. They are lower 128 bytes of RAM, upper 128 bytes of RAM and 128 bytes Special Function Register (SFR). 6.2.1 Lower 128 bytes of RAM: (addresses 0x00 to 0x7F) are accessed by either direct or indirect addressing. ...

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... IFD IFADRH IFADRL 11111111 00000000 00000000 AUXR1 0XXX0XXX TSTWD 0X000000 TL0 TL1 TH0 00000000 00000000 00000000 DPL DPH 00000000 00000000 2/A 3/B 4/C MG87FE/L2051/4051/6051 Preliminary Ver 1.00 5/D 6/E 7/F IFMT SCMD ISPCR XXXX0000 XXXXXXXX 0000XXXX P3WKPE P1WKPE 0X000000 00000000 CKCON XXXXX000 CKCON2 XX001010 IPH 00X00000 ACSR 0XX00000 ...

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... P17WE P16WE P15WE P14WE P13WE P12WE P11WE P10WE D8H D9H CIDL POS2 POS1 POS0 WRF ENW E1H - E2H E3H E4H E5H - - - Note 1 MG87FE/L2051/4051/6051 Preliminary, v 1.03 LSB POF GF1 GF0 PD IDL 9CH 9BH 9AH 89H 88H TR0 IE1 IT1 IE0 IT0 M0 GATE C/T M1 ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 15/56 E6H E7H ISPEN BS SRST CFAIL E8H - - - EAH F0H F7H F6H F5H F4H FAH MG87FE/L2051/4051/6051 Preliminary Ver 1. EBH EAH F3H F2H F1H F0H xxxxxxxxB 0000xxxxB xxxx11xxB 00000000B 00000000B 00000000B ...

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... Port3 Register P3: Port 3 Register Address=B0H, read/write, Power On + RESET=1X11-1111 P37 P36 P35 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 16/56 MG87FE/L2051/4051/6051 VDD 2 clocks delay Strong Input data 4 3 P14 P13 P12 4 3 P34 ...

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... Bit 7, 5~0: P37, P35~P30 could only be set/cleared by CPU. P36 is read only for CPU from analog comparator output. 8.4. Port4 Register P4: Port 4 Register Address=E8H, read/write, Power On + RESET=XXXX-11XX Bit 3~2: P43~P42 could be only be set/cleared by CPU. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 17/56 MG87FE/L2051/4051/6051 P43 P42 Preliminary Ver 1. ...

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... MEGAWIN MAKE YOU WIN 9. Interrupt 9.1. Interrupt Structure This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 18/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 ...

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... When ECF is set, this bit is PTC function. If cleared, this bit is PX3 function. 0: Lower priority, setting with PTCH to select priority level. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 19/56 MG87FE/L2051/4051/6051 ET1 ...

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... IPH: Interrupt Priority High Register Address=B7H, read/write, Power On + RESET=00X0-0000 7 6 PX3H/PTCH PX2H/PACH This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 20/ PT1 PSH PT1H MG87FE/L2051/4051/6051 Preliminary PX1 PT0 PX0 PX1H PT0H PX0H ...

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... There are seven interrupt sources available in MG87FE/L2051/4051/6051. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit(EA), which can be cleared to disable all interrupts at once. Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and the other in IPL (or XICON) register ...

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... The interrupt flag was once active but not serviced is not kept in memory. Each polling cycle is new. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 22/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 ...

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... MAKE YOU WIN 10. Timers/Counters MG87FE/L2051/4051/6051 has two Timers/Counters: Timer 0 and Timer 1. All of them can be configured as timers or event counters. In the “timer” function, the register is incremented every machine cycle. In other words count the machine cycle. Due to 12(6) oscillator periods in a machine cycle, the count rate is 1/12(1/6) of the oscillator frequency. ...

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... TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1 from Timer1. TH0 now controls the Timer1 interrupt. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 24/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 Overflow TLx[7:0] TFx Reload ...

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... Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated). Bit 2: IT1: Interrupt 1 Type control bit. 0: Cleared by software to specify low level triggered external interrupt 1. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 25/56 MG87FE/L2051/4051/6051 GATE C/T ...

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... Bit 0: IT0: Interrupt 0 Type control bit. 0: Cleared by software to specify low level triggered external interrupt 0. 1: Set by software to specify falling edge triggered external interrupt 0. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 26/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 27/56 CCAP0H CCAP0L CL 8-bit Down Counter POS2 POS1 POS0 CPS2 CR MG87FE/L2051/4051/6051 Preliminary Ver 1.00 PWMEN Toggle PWM out Toggle P1.0~P1.7 CPS1 CPS0 ECF CMOD CCON INT3 interrupt vector ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 28/ POS0 CPS2 PWMEN PWM Output Port 1 P1.0 1 P1.1 1 P1.2 1 P1.3 1 P1.4 1 P1.5 1 P1.6 1 P1.7 0 Disabled Pre-scalar 128 MG87FE/L2051/4051/6051 Preliminary CPS1 CPS0 ECF ...

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... CACP0L: PWM-Timer L-Duty Register Address=EAH, read/write, Power On + RESET=0000-0000 CACP0H: PWM-Timer H-Duty Register Address=FAH, read/write, Power On + RESET=0000-0000 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 29/56 MG87FE/L2051/4051/6051 Preliminary Ver 1.00 ...

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... UART The serial port(UART) of MG87FE/L2051/4051/6051 support full-duplex transmission. It can transmit and receive simultaneously. The serial port receive and transmit share the same SFR – SBUF, but actually there is two SBUFs in the chip, one is for transmit and the other is for receive. The serial port can be operated in 4 different modes ...

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... Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 31/ REN TB8 Mode Description Baud Rate 0 shift register F SYSCLK 1 8-bit UART variable 2 9-bit UART F SYSCLK 3 9-bit UART variable MG87FE/L2051/4051/6051 Preliminary Ver 1.00 th received bit indicate that RB8 TI RI /12 / /32 SYSCLK ...

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... Mode 0, or halfway through the stop bit time in the other modes 1100 0000 1111 1101 1100 00x0 The Given slave address will be checked except bit 1 is treated as “don’t care” MG87FE/L2051/4051/6051 Preliminary ...

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... Analog Comparator A single analog comparator is provided in the MG87FE/L2051/4051/6051. The comparator operation is such that the output is a logical “HIGH” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1.1). Otherwise the output is “LOW”. Setting the ACEN bit in ACSR enables the comparator. When the comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds ...

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... Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 34/ ACF ACEN Interrupt Mode Negative (Low) level Positive edge Toggle with de-bounce Positive edge with de-bounce Negative edge Toggle Negative edge with de-bounce Positive (High) level MG87FE/L2051/4051/6051 Preliminary ACM2 ACM1 ACM0 ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 35/56 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 8-bit prescalar WRF - ENW WIDL CLRW CLRW WIDL PS2 MG87FE/L2051/4051/6051 Preliminary Ver 1.00 15-bit timer PS2 PS1 PS0 WDTCR Register 1 0 PS1 PS0 ...

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... Bit 2~0: PS2 ~ PS0, select pre-scalar output for WDT time base input. PS[2: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 36/56 MG87FE/L2051/4051/6051 Pre-scalar Value 128 256 Preliminary, v 1.03 ...

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... L2051/4051/6051 all have four sources of reset: external reset, power-on reset, WDT reset, and software reset. 14.1. Reset Source External Reset POR WDT Reset Software Reset This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 37/56 MG87FE/L2051/4051/6051 Internal Reset Preliminary Ver 1.00 ...

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... MEGAWIN MAKE YOU WIN 15. Power Management MG87FE/L2051/4051/6051 supports two power-reducing modes: Idle and Power-down mode. These two modes are accessed through the PCON register. 15.1. Power Saving Mode 15.1.1. Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator ...

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... Idle should not be one that writes to a port pin or to external memory. 15.1.5. GPIO wake-up Recovery from Power-down The GPIOs of MG87FE/L2051/4051/6051, P1.7 ~ P1.0 and P3.0 ~ P3.5, P3.7 have wake-up CPU capability that are enabled by individual control bit in P1WKPE and P3WKPE. If the interrupt is disabled on P3.2/INT0 or P3 ...

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... Disable port pin wake-up function. 1: Enable port pin wake-up function when port input at falling edge in power-down mode and idle mode. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 40/56 MG87FE/L2051/4051/6051 P14WKP P13WKP ...

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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 41/ System Clock (F ) SYSCLK CLKin CLKin /2 CLKin /4 CLKin /8 CLKin /16 CLKin /32 CLKin /64 CLKin /128 4 3 XCKS4 XCKS3 MG87FE/L2051/4051/6051 Preliminary Ver 1. SCKS2 SCKS1 SCKS0 XCKS2 XCKS1 XCKS0 ...

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... CPU. The access on this bit will affect CKCON2.EN6TR to corresponding operation and get same control function. 0: MG87FE/L2051/4051/6051 will run in 12T mode. 1: MG87FE/L2051/4051/6051 will run in 6T mode. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...

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... Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 43/ Data 4 3 Address 4 3 Address 4 3 Mode Selection Mode Standby AP-memory read AP-memory program AP-memory page erase IAPLB write IAPLB read IAPLB MG87FE/L2051/4051/6051 Preliminary Ver 1. ...

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... The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited. Bit 3~0 : Reserved. MG87FE/L2051/4051/6051 does not make use of idle-mode to perform ISP operation. Instead, it creates CPU wait-state to release flash memory for ISP control circuit use. Once ISP run over, CPU will be waken-up and advanced to the instruction which follows the previous instruction that invokes ISP activity ...

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... ISP operation in field application. The size of IAP flash memory is variable defined by IAPLB. When MG87FE/L2051/4051/6051 boots from AP-memory restricted to have the capability of accessing IAP data flash memory space only. AP-memory and ISP-memory are protected from abnormal disturbance. ...

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... AUXR1: Auxiliary Control Register 1 Address=A2H, read/write, Power On + RESET=0xxx-0xxx P14FD - - Bit 7: P14FD, Enable P14 output with fast driving. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 46/56 MG87FE/L2051/4051/6051 P14FS P13FS P12FS GF2 - Preliminary ...

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... P14 has normal driving on output state. 1: Enable P14 output with fast driving. Bit 6~4: Reserved. Bit 3: GF2, General purpose Flag 2. Bit 2~0: Reserved. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 47/56 MG87FE/L2051/4051/6051 Preliminary Ver 1.00 ...

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... Regarding application not needing high frequency clock recommended for system clock under 40MHz.. EN6T When enabled, MCU will run at 6T mode. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 48/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 ...

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... Exposure to maximum rating conditions for extended periods may affect device reliability. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 49/56 MG87FE/L2051/4051/6051 Preliminary Ver 1.00 Rating Unit -55 ~ +125 °C - 150 ° ...

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... OP I Idle mode current IDLE I Power down current PD R Internal reset pull-down resistance RST This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 50/56 MG87FE/L2051/4051/6051 Limits Test Condition min Typ. 2.0 3 VDD 0 PIN V = 0.4V 20 PIN V =1 ...

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... MEGAWIN MAKE YOU WIN 23. Package Dimension PDIP-20 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 51/56 MG87FE/L2051/4051/6051 Preliminary Ver 1.00 ...

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... MEGAWIN MAKE YOU WIN SOP-20 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 52/56 MG87FE/L2051/4051/6051 Preliminary, v 1.03 ...

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... Add indirect RAM to Acc with Carry ADDC A,#data Add immediate data to Acc with Carry SUBB A,Rn Subtract register from Acc with borrow This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 53/56 MG87FE/L2051/4051/6051 DESCRIPTION Preliminary Ver 1.00 BYTE EXECUTION TIME(MC ...

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... Swap nibbles within the Acc BOOLEAN VARIABLE MANIPULATION CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 54/56 MG87FE/L2051/4051/6051 Preliminary ...

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... DJNZ Rn,rel Decrement register and jump if not equal DJNZ direct,rel Decrement direct byte and jump if not equal NOP No Operation This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 55/56 MG87FE/L2051/4051/6051 Preliminary Ver 1. ...

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... V1.03 1. Page-5, modified order information, MG87Fxy051AE 2. Page-5, modified order information, MG87Fxy051AS 3. Page-33, comparator structure diagram modify input pin name. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 56/56 MG87FE/L2051/4051/6051 Descriptions PWM-Timer MG87Fxy051AE20 MG87Fxy051AS20 Preliminary, v 1.03 2009/FEB/14 ...