MPC2F35E2 MEGAWIN [Megawin Technology Co., Ltd], MPC2F35E2 Datasheet - Page 10

• Manufacturer Part Number: MPC2F35E2
• Description: Low-speed USB micro-controller
• Manufacturer: MEGAWIN [Megawin Technology Co., Ltd]

System Control Registers
Power saving control
When the low-voltage detector is enabled, and if it senses the power voltage is lower than 3.3V, then
MPC2F35 will be reset automatically.
Programmer can switch the normal operation mode to the power-saving mode for reducing power
consumption through this register. There are two power saving modes in MPC2F35.
Stop mode: (PWR_CTL.
System clock stops the built-in oscillator if setting the CKC bit in the PWR_CTL SFR. MPC2F35 can be
awakened from the stop mode by 4 ways: the port 3 interrupt, the hardware reset, the power-on reset
and the USB wake-up.
Halt mode: (PWR_CTL.
Setting the HALT bit to let the clock source of MPC2F35 to be in the off-line status, but the oscillator
works or not will be depended on the content of the CKC bit in the PWR_CTL SFR.
MPC2F35 can be awakened from the halt mode by 3 ways: the interrupts (USB, Timer 0, Port3, INT0
and INT1) can be assigned by the RLH_EN register, the hardware reset, or the power-on reset.
F
10
CPU
Address
Address
0200H
LVDT: Low-voltage detector disable bit. 1: Disable, 0: Enable (default)
CKC: Oscillator control bit. 1: Disable OSC, 0: Enable OSC (default)
HALT: FCPU off-line control bit. 1: FCPU off-line, 0: FCPU on-line (default)
selector
PWR_CTL
Name
Name
Fosc/2^18
HALT
CKC
LVDT
Bit 7
Bit 7
= 1)
= 1)
Qw1 Qw2
R
MPC2F35_USB Data Sheet
Bit 6
Bit 6
WDT
R
-
Qw3
R
Qw4
Bit 5
Bit 5
R
-
Overflow signal
Bit 4
Bit 4
S
R
-
Q
Bit 3
Bit 3
-
System Reset
WDT_ST.7
Hardware reset
Bit 2
Bit 2
WDT_CLR.7
-
CKC
Bit 1
Bit 1
MEGAWIN
HALT
Bit 0
Bit 0
R
R
-
W
W
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