CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 8

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Figure 2-7
performance on a two layer board.
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
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For information on circuit board layout issues for mixed signals, refer to the application note
Layout Considerations for PSoC® 3 and PSoC 5.
Document Number: 001-56955 Rev. *N
Note
11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in
page 29. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
(Configurable XRES, GPIO) P1[2]
(TCK, SWDCK, GPIO) P1[1]
(TMS, SWDIO, GPIO) P1[0]
and
(TDO, SWV, GPIO) P1[3]
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
(NTRST, GPIO) P1[5]
Figure 2-8
(TDI, GPIO) P1[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
VBOOST
show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
VSSB
VSSD
XRES
VBAT
IND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Lines show VDDIO
to I/O supply
association
Figure 2-6. 100-pin TQFP Part Pinout
TQFP
PSoC
AN57821 - Mixed Signal Circuit Board
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Figure 2-7
®
3: CY8C32 Family
VDDIO0
P0[3] (GPIO,EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
and
Data Sheet
Power System
Page 8 of 122
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