CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet
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CY8C32_12
Manufacturer Part Number
CY8C32_12
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C32_12.pdf
(122 pages)
General Description
With its unique array of configurable blocks, PSoC
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. *N
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Single cycle 8051 CPU core
Low voltage, ultra low-power
Versatile I/O system
Digital peripherals
DC to 50 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
512-byte flash cache
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V through 1.8-V to
5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
• 200-nA hibernate mode with RAM retention
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments
CapSense
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
16 to 24 programmable PLD based universal digital
blocks (UDB)
low-voltage detect (LVD) interrupt
[1]
bus access
®
[2]
support from any GPIO
)
Ordering Information
[3]
•
198 Champion Court
Programmable System-on-Chip (PSoC
®
3 is a true system level solution providing microcontroller unit (MCU), memory,
on page 107 for details.
[2]
Analog peripherals (1.71 V V
Programming, debug, and trace
Precision, programmable clocking
Temperature and packaging
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
1.024 V ±0.9-percent internal voltage reference across –40°C
to +85°C
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
One 8-bit, 8-Msps IDAC or 1-Msps VDAC
Two comparators with 95 ns response time
CapSense support
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
4-KB instruction trace buffer
Bootloader programming supportable through I
UART, USB, and other interfaces
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
transmitter receiver (UART), and I
ratio (SINAD), ±1-bit INL/DNL
•
San Jose
2
C). In addition to communication interfaces,
PSoC
,
CA 95134-1709
®
DDA
3: CY8C32 Family
5.5 V)
2
Revised June 18, 2012
C
•
Data Sheet
408-943-2600
2
C, SPI,
®
)
[2]