FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 175

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FWIXEPAD0SE001

Manufacturer Part Number
FWIXEPAD0SE001
Description
Advanced 8-Port 10/100 Mbps PHY Transceivers
Manufacturer
INTEL [Intel Corporation]
Datasheet
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 59. Intel
Peak differential output voltage
Link transmit period
Jitter magnitude added by the
MAU and PLS sections
Receive input impedance
Link min receive timer
Link max receive timer
Differential squelch threshold
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
4. After line model specified by IEEE 802.3 for 10BASE-T MAU.
testing.
ns from the MAU.
®
LXT9785/LXT9785E 10BASE-T Transceiver Characteristics
Parameter
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3, 4
3
TLR
TLR
Sym
V
t
V
Z
tx-jit
OP
DS
IN
max
min
Min
2.2
50
Transmitter
8
2
Receiver
Typ
100
475
2.5
1
Max
150
2.8
24
11
7
mV Peak
Units
ms
ms
ms
ns
W
V
Between TPFIP and
5 MHz square wave
Test Conditions
Note 2
TPFIN
input
177

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