FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 117

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.2.1.2
4.2.1.3
4.3
4.3.1
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Table 40. Intel
Note: The BGA15 package does not support MDIX hardware configuration. Software must be used to
Note: The BGA15 package does not support the fiber interface.
Note: The BGA15 package does not support the RMII interface.
During 10 Mbps operation, LXT9785/LXT9785E encoded data is exchanged. When no data are
being exchanged, the line is left in an idle state with NLPs transmitted to maintain link.
MDI Crossover (MDIX)
The LXT9785/LXT9785E crossover function, which is compliant to the IEEE 802.3, clause 23
standard, connects the transmit output of the device to the far-end receiver in a link segment. This
function can be disabled via Register bits 27.9:8 or by using the hardware configuration pins.
control the function after power-up.
Fiber Interface
The LXT9785/LXT9785E fiber ports are designed to interface with common industry-standard 3.3
V and 5 V fiber-optic transceivers. Each of the 8 ports incorporates a Low-Voltage PECL interface
that complies with the ANSI X3.166 standard for seamless integration.
Fiber mode is selected through Register bit 16.0 by the following two methods:
The fiber interface is capable of full-duplex or half-duplex operation. In half duplex, operation
collisions must be managed by external Layer 2 logic (MAC). Auto negotiation is not supported for
fiber mode.
Media Independent Interface (MII) Interfaces
The LXT9785/LXT9785E supports Reduced MII or Serial MII, but not concurrently. The interface
mode selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports.
Refer to
Global MII Mode Select
The mode select pins are used for MII interface configuration settings upon power-up sequencing.
All ports are configured the same and cannot be intermixed.
1. Configure Register bit 16.0 = 1 on a global basis (all 8 ports) by driving the Hardware Control
2. Configure Register bit 16.0 = 1 on a per-port basis through the MDIO interface.
AMDIX_EN
pin G_FX/TP to a logic High value on power-up and/or reset.
®
LXT9785/LXT9785E MDIX Selection
0
0
1
Table 41
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
for the mode select settings.
MDIX
X
0
1
Auto MDI/MDIX
MDIX forced
MDIX Mode
MDI forced
119