FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 3

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Contents
1.0
2.0
3.0
4.0
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Introduction.................................................................................................................................. 18
1.1
1.2
Block Diagram ............................................................................................................................. 19
Pin/Ball Assignments and Signal Descriptions ........................................................................ 20
3.1
3.2
3.3
3.4
3.5
3.6
Functional Description..............................................................................................................116
4.1
4.2
4.3
What You Will Find in This Document ................................................................................ 18
Related Documents ............................................................................................................ 18
PQFP Pin Assignments ...................................................................................................... 20
3.1.1
3.1.2
3.1.3
PQFP Signal Descriptions .................................................................................................. 36
3.2.1
3.2.2
BGA23 Ball Assignments.................................................................................................... 51
3.3.1
3.3.2
3.3.3
BGA23 Signal Descriptions ................................................................................................ 82
3.4.1
3.4.2
BGA15 Ball Assignments.................................................................................................... 98
3.5.1
BGA15 Signal Descriptions ..............................................................................................109
3.6.1
3.6.2
Introduction .......................................................................................................................116
4.1.1
4.1.2
Interface Descriptions .......................................................................................................117
4.2.1
Media Independent Interface (MII) Interfaces...................................................................119
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
PQFP Pin Assignments – RMII Configuration ....................................................... 21
PQFP Pin Assignments – SMII Configuration........................................................ 26
PQFP Pin Assignments – SS-SMII Configuration.................................................. 31
Signal Name Conventions ..................................................................................... 36
PQFP Signal Descriptions – RMII, SMII, and SS-SMII Configurations.................. 36
RMII BGA23 Ball List ............................................................................................. 52
SMII BGA23 Ball List ............................................................................................. 62
SS-SMII BGA23 Ball List ....................................................................................... 72
Signal Name Conventions ..................................................................................... 82
Signal Descriptions – RMII, SMII, and SS-SMII Configurations............................. 82
BGA15 Ball List...................................................................................................... 99
Signal Name Conventions ...................................................................................109
Signal Descriptions – SMII and SS-SMII Configurations .....................................109
OSP™ Architecture .............................................................................................116
Comprehensive Functionality ..............................................................................117
4.1.2.1
10/100 Network Interface.....................................................................................117
4.2.1.1
4.2.1.2
4.2.1.3
Global MII Mode Select .......................................................................................119
Internal Loopback ................................................................................................120
RMII Data Interface..............................................................................................120
Serial Media Independent Interface (SMII) and Source Synchronous-
Serial Media Independent Interface (SS-SMII) ....................................................121
4.3.4.1
4.3.4.2
Configuration Management Interface ..................................................................121
MII Isolate ............................................................................................................121
Sectionalization ....................................................................................117
Twisted-Pair Interface ..........................................................................118
MDI Crossover (MDIX).........................................................................119
Fiber Interface......................................................................................119
SMII Interface.......................................................................................121
Source Synchronous-Serial Media Independent Interface ..................121
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