FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 14

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

Contents
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49
70
1
Description
Modified
Modified
Modified
Modified
Modified
Modified
Modified
Modified
Modified
SC to R/LH.
Modified
Modified
Register bit 25.0.
Modified
Modified
Description
Added bullet to Product Features
Modified Table 12 “Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions” (Added
FIFOSEL1 and FIFOSEL0)
Added Section 2.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced
Speed Mode”
Modified Figure 38 “Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver
Interface Circuitry”
Added Figure 39 “Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Circuitry”
Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”
Modified Table 28 “Absolute Maximum Ratings”
Modified Table 29 “Operating Conditions”
Modified Table 31 “Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)”(Output low
voltage SD pins - Max)
Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX
Receive Timing Parameters”
Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX
Receive Timing Parameters”
Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive
Timing Parameters”
Table 83 “Control Register (Address
Table 84 “Status Register (Address
Table 87 “Auto-Negotiation Advertisement Register (Address
Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address
Table 91 “Auto-Negotiation Link Partner Next Page Receive Register (Address
Table 92 “Port Configuration Register (Address 16, Hex
Table 93 “Quick Status Register (Address 17, Hex
Table 94 “Interrupt Enable Register (Address 18, Hex 12)”
Table 95 “Interrupt Status Register (Address 19, Hex
Table 97 “Receive Error Count Register (Address 21, Hex
Table 98 “RMII Out-of-Band Signaling Register (Address 25, Hex
Table 99 “Trim Enable Register (Address 27, Hex
Table 103 “Product
Revision Number: 006 (INTERNAL RELEASE)
Information”.
Revision Date: June 10, 2003
Revision Date: January 2002
Revision Number: 005
1)”.
0)”.
1B)”.
11)”.
13)”. Changed all references of RO/
10)”.
15)”.
4)”.
Revision Date: August 28, 2003
19)”. Added note to
Document Number: 249241
Revision Number: 007
5)”.
Datasheet
8)”.