FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 125

• Manufacturer Part Number: FWIXEPAD0SE001
• Description: Advanced 8-Port 10/100 Mbps PHY Transceivers
• Manufacturer: INTEL [Intel Corporation]

4.5.3
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
Figure 13. Intel
Note: The BGA15 package does not support the PWRDWN pin feature.
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible.
The device can be put into a low-power state via Register 0 as well as a near-zero power state with
the power down pin. When in power-down mode, the device is not capable of receiving or
transmitting packets.
The lowest power operation is achieved using the Global power-down pin, which is active High.
This pin powers down every circuit in the device, including all clocks. All registers are unaltered
and maintained when the Global PWRDWN pin is released.
Individual ports (software power down) can be powered down using Register bit 0.11. This bit
powers down a significant portion of the port, but clocks to the register section remain active. This
allows the management interface to remain active during register power-down. The power-down
bit is active High.
®
LXT9785/LXT9785E Initialization Sequence
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Reset MDIO Registers to
Control Interface at last
Pass Control to MDIO
MDIO Control
values read at H/W
Hardware Reset
Mode
Interface
Software
Reset?
Yes
Low
Initialize MDIO Registers
Power-up or Reset
Read H/W Control
MDDIS Voltage
Interface
Level?
Disable MDIO Writes
High
Hardware Control
Hardware
Reset?
Mode
Yes
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