FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet - Page 176
FWIXEPAD0SE001
Manufacturer Part Number
FWIXEPAD0SE001
Description
Advanced 8-Port 10/100 Mbps PHY Transceivers
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.FWIXEPAD0SE001.pdf
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
178
Figure 39. Intel
Table 60. Intel
RxData output delay from REFCLK
rising edge
RxData Rise/Fall Time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-
asserted
SYNC setup to REFCLK rising edge
SYNC hold from REFCLK rising edge
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
REFCLK
testing.
100BASE-TX or 100BASE-FX).
®
RxData
®
SYNC
LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters
LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
TPFI
default configuration of 00 (32 bits of initial fill).
Parameter
t
3
t
5
Sym
t1
t2
t3
t4
t5
t6
t
6
Min
1.5
1.5
1.0
–
–
–
t
Typ
1
1.0
21
25
–
–
–
1
Max
29
30
5
–
–
–
t
2
Units
BT
BT
ns
ns
ns
ns
2
2
Revision Date: August 28, 2003
Minimum C
Maximum C
Synchronous sampling of
SMII
Synchronous sampling of
SMII
Document Number: 249241
t
Test Conditions
4
Revision Number: 007
L
L
= 5 pF
–
–
–
= 20 pF
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