SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 82

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
10.4.1
If the data output is enabled at the expansion port, then the
data stream from the decoder is present. The data format
of the 8-bit data bus is dependent on the chosen data type
which is selectable by the line control registers LCR2
to LCR24; see Table 17. In contrast to the image port, the
sliced data format is not available on the expansion port.
Instead, raw CVBS samples are always transferred if any
sliced data type is selected.
Details of some of the data types on the expansion port are
as follows:
Table 42 Data format on the expansion port
Notes
1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’; see Table 173. In
2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced
2004 Jun 29
...
BLANKING
Active video: (data type 15) contains components
Y-C
amplitude and offsets are programmable via
DBRI7 to DBRI0, DCON7 to DCON0,
DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and
OFFV0. For nominal levels see Fig.26.
Test line: (data type 6) is similar to the active video
format, with some constraints within the data
processing:
– adaptive chrominance comb filter, vertical filter
– adaptive luminance comb filter, peaking and
This data type is defined for future enhancements. It can
be activated for lines containing standard test signals
within the vertical blanking period. Currently most
sources do not contain test lines. For nominal levels
see Fig.26.
HD-CODEC
PERIOD
this event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.
by CVBS samples.
(chrominance comb filter for NTSC standards, PAL
phase error correction) within the chrominance
processing are disabled
chrominance trap are bypassed within the luminance
processing.
80 10 FF 00 00 SAV C
B
-C
X
R
PORT CONFIGURED AS OUTPUT
4 : 2 : 2 signal, 720 active pixels per line. The
CODE (HEX)
REFERENCE
TIMING
(1)
B
0 Y0 C
720 PIXELS Y-C
R
0 Y1 C
B
B
82
-C
2 Y2 ... C
R
The relationship of LCR programming to line numbers is
described in Section 9.2; see Tables 18 to 21.
The data type selections by LCR are overruled by setting
OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly
intended for device production testing. The VPO-bus
carries the upper or lower 8 bits of the two ADCs
depending on the OFTS[1:0] 13H[1:0] settings; see
Table 173. The output configuration is done via
MODE[3:0] 02H[3:0] settings; see Table 155. If a Y/C
mode is selected, the expansion port carries the
multiplexed output signals of both ADCs, in CVBS mode
the output of only one ADC. No timing reference codes are
generated in this mode.
Remark: The LSBs (bit 0) of the ADCs are also available
on pin RTS0; see Table 171.
The SAV/EAV timing reference codes define the start and
end of valid data regions. The ITU-blanking code
sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the
horizontal blanking period, between EAV and SAV.
The position of the F bit is constant according to ITU 656;
see Tables 44 and 45.
The V bit can be generated in two different ways (see
Tables 44 and 45) controlled via OFTS1 and OFTS0; see
Table 173.
F and V bits change synchronously with the EAV code.
4 : 2 : 2 DATA
Raw samples (data types 0 to 5 and 7 to 14): C
samples are similar to data type 6, but CVBS samples
are transferred instead of processed luminance samples
within the Y time slots.
The amplitude and offset of the CVBS signal is
programmable via RAWG7 to RAWG0 and
RAWO7 to RAWO0, see Chapter 18,
Tables 178 and 179. For nominal levels see Fig.27.
R
718 Y719 FF 00 00 EAV 80 10 ...
SAA7108AE; SAA7109AE
(2)
CODE (HEX)
REFERENCE
TIMING
Product specification
(1)
BLANKING
PERIOD
B
-C
R