SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 27

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
8.18
The I
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are read and
write, except two read only status bytes.
The register bit map consists of an RGB Look-Up Table
(LUT), a cursor bit map and control registers. The LUT
contains three banks of 256 bytes, where each RGB triplet
is assigned to one address. Thus a write access needs the
LUT address and three data bytes following subaddress
FFH. For further write access auto-incrementing of the
LUT address is performed. The cursor bit map access is
similar to the LUT access but contains only a single byte
per address.
The I
8.19
In order to reduce the power consumption, the
SAA7108AE; SAA7109AE supports 2 Power-down
modes, accessible via the I
Power-down mode (DOWNA = 1) turns off the
digital-to-analog converters and the pixel clock
synthesizer. The digital down mode turns off all internal
clocks and sets the digital outputs to LOW except the
I
still be accessed in this mode, but not all registers can be
read from or written to. Reading or writing to the look-up
tables, the cursor and the HD sync generator require a
valid pixel clock. The typical supply current in full
power-down is approximately 5 mA.
Due to the fact that the analog Power-down mode turns off
the pixel clock synthesizer, there are limitations in some
applications. If there is no pixel clock, the IC is not able to
set its outputs to LOW.
2004 Jun 29
2
Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM)
00
CC 00
80 00
0A 00
CC 00
80 00
Write to subaddress DCH
0B
C-bus interface. The IC retains its programming and can
HD-CODEC
2
2
C-bus interface is a standard slave transceiver,
C-bus slave address is defined as 88H.
I
Power-down modes
SEQUENCE
2
C-bus interface
2
C-bus. The analog
points to first entry of value array (index 0)
black level, to be added during active video
sync level LOW (minimum output voltage)
sync level HIGH (3-level sync)
black level (needed elsewhere)
null (identical with sync level LOW)
insertion is active, gain for signal is adapted accordingly
27
So in most cases, DOWNA and DOWND should be set to
logic 1 simultaneously. If the EIDIV bit is logic 1, it should
be set to logic 0 before power-down.
8.20
The encoder section needs to provide a continuous data
stream at its analog outputs as well as receive a
continuous stream from its data source. Due to the fact
that there is no frame memory isolating the data streams,
restrictions apply to the input frame timings.
Input and output processing of the encoder section are
only coupled through the vertical frequencies. In master
mode, the encoder provides a vertical sync and an
odd/even pulse to the input processing, in slave mode, the
encoder receives them.
The parameters of the input field are mainly given by the
memory capacity of the encoder section. The rule is that
the scaler and thus the input processing needs to provide
the video data in the same time frames as the encoder
reads them. So the vertical active video times (and the
vertical frequencies) need to be the same.
The second rule is that there has to be data in the buffer
FIFO when the encoder enters the active video area.
So the vertical offset in the input path needs to be a bit
shorter than the offset of the encoder.
The following gives the set of equations required to
program the IC for the most common application: A post
processor in master mode with non-interlaced video input
data.
COMMENT
Programming the graphics acquisition scaler
of the video encoder
SAA7108AE; SAA7109AE
Product specification