SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 127

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 104 Logic levels and function of PCLE
Table 105 Logic levels and function of PCLI
Table 106 Subaddress 85H
Table 107 Subaddresses 90H and 94H
Table 108 Subaddresses 91H and 94H
Table 109 Subaddresses 92H and 94H
2004 Jun 29
EIDIV
FILI
XOFS
XPIX
YOFSO
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
HD-CODEC
PCLE1
PCLI1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
PCLE0
LOGIC
LEVEL
PCLI0
0
1
0
1
0
1
0
1
0
1
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2; default after reset
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
divider ratio for internal PIXCLK is 1
divider ratio for internal PIXCLK is 2; default after reset
divider ratio for internal PIXCLK is 4
not allowed
input dividers are off; inputs are high-impedance; default after reset
input dividers are on; inputs have lower impedance
threshold for FIFO internal transfers; nominal value is 8; default after reset
127
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7108AE; SAA7109AE
Product specification