ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 40

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
JTAG Test and Emulation Port Timing
Table 30
Table 30. JTAG Port Timing
1
2
3
Parameter
Timing Parameters
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs= DATA31–0, ARDY, PF47–0, PPI0CLK, PPI1CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
50 MHz maximum
System Outputs = DATA31–0, ADDR25–2, ABE3–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3–0, PF47–0, RSCLK0–1, RFS0–1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
RESET, NMI0, NMI1, BMODE1–0, BR, and PPIxD7–0.
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, and PPIxD7–0.
and
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
Figure 26
TCK
TMS
TDO
SYSTEM
OUTPUTS
INPUTS
TDI
SYSTEM
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
1
t
3
SSYS
1
t
STAP
Rev. B | Page 40 of 64 | June 2007
t
TCK
Figure 26. JTAG Port Timing
t
HSYS
t
HTAP
Min
20
4
4
4
5
4
0
Max
10
12
Unit
ns
ns
ns
ns
ns
TCK
ns
ns