ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 4

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
MEMORY ARCHITECTURE
The ADSP-BF561 views memory as a single unified 4G byte
address space, using 32-bit addresses. All resources including
internal memory, external memory, and I/O control registers
occupy separate sections of this common address space. The
memory portions of this address space are arranged in a hierar-
chical structure to provide a good cost/performance balance of
some very fast, low latency memory as cache or SRAM very
close to the processor, and larger, lower cost and performance
memory systems farther away from the processor. The
ADSP-BF561 memory map is shown in
The L1 memory system in each core is the highest performance
memory available to each Blackfin core. The L2 memory pro-
vides additional capacity with lower performance. Lastly, the
off-chip memory system, accessed through the External Bus
Interface Unit (EBIU), provides expansion with SDRAM, flash
memory, and SRAM, optionally accessing more than
768M bytes of physical memory. The memory DMA controllers
provide high bandwidth data movement capability. They can
perform block transfers of code or data between the internal
L1/L2 memories and the external memory spaces.
DA1
DA0
LD1
LD0
SD
32
32
32
32
32
R1.H
R0.H
R7.H
R6.H
R3.H
R2.H
R5.H
R4.H
RAB
32
R0.L
R7.L
R2.L
R1.L
I3
I2
R6.L
R5.L
R4.L
R3.L
I1
I0
32
Figure
L3
L2
L1
L0
32
BARREL
SHIFTER
3.
B3
B2
B1
B0
8
Rev. B | Page 4 of 64 | June 2007
ADDRESS ARITHMETIC UNIT
32
Figure 2. Blackfin Processor Core
M3
M2
M1
M0
A0
DATA ARITHMETIC UNIT
16
40
32
DAG1
8
40
40
Internal (On-Chip) Memory
The ADSP-BF561 has four blocks of on-chip memory providing
high bandwidth access to the core.
The first is the L1 instruction memory of each Blackfin core
consisting of 16K bytes of four-way set-associative cache mem-
ory and 16K bytes of SRAM. The cache memory may also be
configured as an SRAM. This memory is accessed at full proces-
sor speed. When configured as SRAM, each of the two 16K
banks of memory is broken into 4K sub-banks which can be
independently accessed by the processor and DMA.
The second on-chip memory block is the L1 data memory of
each Blackfin core which consists of four banks of 16K bytes
each. Two of the L1 data memory banks can be configured as
one way of a two-way set-associative cache or as an SRAM. The
other two banks are configured as SRAM. All banks are accessed
at full processor speed. When configured as SRAM, each of the
four 16K banks of memory is broken into 4K sub-banks which
can be independently accessed by the processor and DMA.
The third memory block associated with each core is a 4K byte
scratchpad SRAM which runs at the same speed as the L1 mem-
ories, but is only accessible as data SRAM (it cannot be
configured as cache memory and is not accessible via DMA).
8
DAG0
16
40
A1
ASTAT
SP
P5
P3
P2
P1
P0
FP
P4
8
32
PREG
LOOP BUFFER
SEQUENCER
DECODE
CONTROL
ALIGN
UNIT