ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 2

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
TABLE OF CONTENTS
General Description ................................................. 3
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Portable Low Power Architecture ............................. 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Watchdog Timer .................................................. 8
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ......................... 9
UART Port .......................................................... 9
Programmable Flags (PFx) .................................... 10
Parallel Peripheral Interface ................................... 10
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 14
Development Tools ............................................. 15
Designing an Emulator-Compatible Processor Board .. 16
Related Documents ............................................. 16
Operating Conditions .......................................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings .................................. 21
Package Information ........................................... 21
ESD Sensitivity ................................................... 21
Timing Specifications .......................................... 22
Voltage Regulator Layout Guidelines .................... 12
Clock and Reset Timing .................................... 23
Asynchronous Memory Read Cycle Timing ........... 24
Asynchronous Memory Write Cycle Timing .......... 25
SDRAM Interface Timing .................................. 26
External Port Bus Request and Grant Cycle Timing .. 27
Parallel Peripheral Interface Timing ..................... 28
Serial Ports ..................................................... 32
Serial Peripheral Interface (SPI) Port—
Serial Peripheral Interface (SPI) Port—
Universal Asynchronous Receiver Transmitter (UART)
Master Timing ............................................. 35
Slave Timing ............................................... 36
Port—Receive and Transmit Timing ................. 37
Rev. B | Page 2 of 64 | June 2007
256-Ball CSP_BGA Ball Assignment ........................... 46
256-Ball CSP_BGA Ball Assignment ........................... 51
297-Ball PBGA ball assignment .................................. 56
Outline Dimensions ................................................ 61
Ordering Guide ..................................................... 64
REVISION HISTORY
4/07—Changes from Rev. A to Rev. B
Added Text to
Changed Font in Formula in
Complete Rewrite of
Complete Rewrite of
Edit to Figure
Edit to Figure
Deleted References to Temperature in Figures
Moved Data to Operating Conditions
Deleted References to Temperature in Figures
Added figures for
View) ....................................................................50
Added figure
(CSP_BGA) (BC-256-4).............................................61
Added Models to
5/06—Changes from Rev. 0 to Rev. A
1/05—Initial version
in
and Rewrote
in
Output Drive Currents ......................................... 41
Power Dissipation ............................................... 42
Test Conditions .................................................. 42
Environmental Conditions .................................... 44
Output Drive Currents ..........................................41
Test Conditions ...................................................42
Programmable Flags Cycle Timing ....................... 38
Timer Cycle Timing .......................................... 39
JTAG Test and Emulation Port Timing .................. 40
256-Ball Chip Scale Package Ball Grid Array
Power Dissipation ..................................42
Asynchronous Memory Read Cycle Timing .24
Asynchronous Memory Write Cycle Timing 25
Serial Ports (SPORTs) ............................. 9
Ordering Guide ................................64
256-Ball CSP_BGA Ball Configuration (Top
Operating Conditions ....................20
Electrical Characteristics ................20
Power Savings ...................12