ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 17

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

PIN DESCRIPTIONS
ADSP-BF561 pin definitions are listed in
maintain maximum function and reduce package size and pin
count, some pins have multiple functions. In cases where pin
function is reconfigurable, the default state is shown in plain
text, while alternate functionality is shown in italics.
Table 8. Pin Descriptions
Pin Name
EBIU
EBIU (ASYNC)
EBIU (SDRAM)
ADDR25–2
DATA31–0
ABE3–0/SDQM3–0
BR
BG
BGH
AMS3–0
ARDY
AOE
AWE
ARE
SRAS
SCAS
SWE
SCKE
SCLK0/CLKOUT
SCLK1
SA10
SMS3–0
Type Function
O
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled HIGH if not used.)
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control (This pin should be pulled HIGH if not used.)
Output Enable
Write Enable
Read Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output Pin 0
Clock Output Pin 1
SDRAM A10 Pin
Bank Select
Table
8. In order to
Rev. B | Page 17 of 64 | June 2007
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface. On the
external memory interface, the control and address lines are
driven high during reset unless the BR pin is asserted.
All I/O pins have their input buffers disabled, with the exception
of the pins noted in the data sheet that need pull-ups or pull-
downs if unused.
ADSP-BF561
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
A
A
1