ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

ADSP-BF561
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 6. Core Clock Ratios
The maximum PLL clock time when a change is programmed
via the PLL_CTL register is 40 μs. The maximum time to change
the internal voltage via the internal voltage regulator is also
40 μs. The reset value for the PLL_LOCKCNT register is 0x200.
This value should be programmed to ensure a 40 μs wakeup
time when either the voltage is changed or a new MSEL value is
programmed. The value should be programmed to ensure an
80 μs wakeup time when both voltage and the MSEL value are
changed. The time base for the PLL_LOCKCNT register is the
period of CLKIN.
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in
automatically loading internal L1 instruction memory, L2, or
external memory after a reset. A fourth mode is provided to exe-
cute from external memory, bypassing the boot sequence.
Table 7. Booting Modes
The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:
Signal Name
CSEL1–0
00
01
10
11
BMODE1–0 Description
00
01
10
11
• Execute from 16-bit external memory – Execution starts
• Boot from 8-bit/16-bit external flash memory – The
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time,
15-cycle R/W access times, 4-cycle setup). Note that, in
bypass mode, only Core A can execute instructions from
external memory.
8-bit/16-bit flash boot routine located in boot ROM mem-
ory space is set up using Asynchronous Memory Bank 0.
6. This programmable core clock capability is useful for
Execute from 16-bit external memory
(Bypass Boot ROM)
Boot from 8-bit/16-bit flash
Boot from SPI host slave mode
Boot from SPI serial EEPROM
(16-, 24-bit address range)
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Example Frequency
Ratios (MHz)
VCO
500
500
200
200
CCLK
500
250
50
25
Table
Rev. B | Page 14 of 64 | June 2007
7) for
For each of the boot modes, a boot loading protocol is used to
transfer program and data blocks from an external memory
device to their specified memory locations. Multiple memory
blocks may be loaded by any boot sequence. Once all blocks are
loaded, Core A program execution commences from the start of
L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-
off state until Bit 5 of SICA_SYSCR is cleared by Core A. After
that, Core B will start execution at address 0xFF60 0000.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax that was designed for ease of coding
and readability. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles
to a very small final memory size. The instruction set also pro-
vides fully featured multifunction instructions that allow the
programmer to use many of the processor core resources in a
single instruction. Coupled with many features more often seen
on microcontrollers, this instruction set is very efficient when
compiling C and C++ source code. In addition, the architecture
supports both a user (algorithm/application code) and a super-
visor (O/S kernel, device drivers, debuggers, ISRs) mode of
operation—allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Boot from SPI host device – The Blackfin processor oper-
• Boot from SPI serial EEPROM (16-, 24-bit addressable) –
• Seamlessly integrated DSP/CPU features are optimized for
• A multi-issue load/store modified Harvard architecture,
All configuration settings are set for the slowest device pos-
sible (3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
The SPI uses the PF2 output pin to select a single SPI
EPROM device, submits a read command at address
0x0000, and begins clocking data into the beginning of L1
instruction memory. A 16-, 24-bit addressable SPI-compat-
ible EPROM must be used.
both 8-bit and 16-bit operations.
which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.