ADSP-BF561SBBCZ-5A2 AD [Analog Devices], ADSP-BF561SBBCZ-5A2 Datasheet - Page 25

• Manufacturer Part Number: ADSP-BF561SBBCZ-5A2
• Manufacturer: AD [Analog Devices]

Asynchronous Memory Write Cycle Timing
Table 18. Asynchronous Memory Write Cycle Timing
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.
SARDY
HARDY
DDAT
ENDAT
DO
HO
ADDR19–1
DATA15–0
CLKOUT
ABE1–0
AMSx
ARDY
AWE
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
DATA31–0 Disable After CLKOUT
DATA31–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
SETUP
END AT
t
DO
t
DO
ABE, ADDRESS
WRITE DATA
t
1
1
SARDY
PROGRAMMED WRITE
ACCESS 2 CYCLES
Figure 10. Asynchronous Memory Write Cycle Timing
Rev. B | Page 25 of 64 | June 2007
t
SARDY
EXTENDED
1 CYCLE
ACCESS
t
HO
t
HARDY
1 CYCLE
HOLD
t
HO
Min
4.0
0.0
1.0
0.8
t
DD AT
Max
6.0
6.0
ADSP-BF561
Unit
ns
ns
ns
ns
ns
ns