DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 257
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DSP56303
Manufacturer Part Number
DSP56303
Description
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.DSP56303.pdf
(292 pages)
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Freescale Semiconductor
Application:
PLL Control Register (PCTL)
Reset = $000000
23 22 21 20
PD3
PLL
PD3–PD0
PD2
$0
$1
$2
$F
Predivision Factor Bits (PD0–PD3)
•
•
•
Clock Output Disable (COD)
0 = 50% Duty Cycle Clock
1 = Pin Held In High State
PD1
PSTP
PD0
0
1
1
Figure B-4. Phase-Locked Loop Control Register (PCTL)
Predivision Factor PDF
19 18 17 16
COD
PEN
PSTP and PEN Relationship
1
0
1
PEN
16
1
2
3
•
•
•
Disabled
Disabled
Enabled
PSTP
Operation During STOP
PLL
XTLD XTLR DF2
Disabled
Enabled
Enabled
15 14 13 12 11 10 9
DSP56303 User’s Manual, Rev. 2
Oscillator
X:$FFFFFD Read/Write
DF1
XTAL Disable Bit (XTLD)
0 = Enable Xtal Oscillator
1 = EXTAL Driven From
DF0 MF11
An External Source
1 = External Xtal Freq < 200KHz
0 = External Xtal Freq > 200KHz
Crystal Range Bit (XTLR)
MF10 MF9 MF8
DF2–DF0
8
$0
$1
$2
$7
•
•
•
Division Factor Bits (DF0–DF2)
MF7
7
MF11–MF0
$000
$001
$002
$FFF
$FFF
MF6
Date:
Programmer:
Multiplication Factor Bits MF0–MF11
•
•
•
6
MF5 MF4 MF3 MF2 MF1 MF0
5
Division Factor DF
4
Multiplication Factor MF
2
2
2
2
•
•
•
0
1
2
7
3
4095
4096
Sheet 1 of 1
2
Programming Sheets
1
2
3
•
•
•
1
0
B-13