AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 62
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AD9148BPCZ
Manufacturer Part Number
AD9148BPCZ
Description
Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
Manufacturer
AD [Analog Devices]
Datasheet
1.AD9148BPCZ.pdf
(73 pages)
- Current page: 62 of 73
- Download datasheet (852Kb)
AD9148
Reducing LO Leakage and Unwanted Sidebands
Analog Devices modulators can introduce unwanted signals at
the LO frequency due to dc offset voltages in the I and Q baseband
inputs as well as feedthrough paths from the LO input to the
output. The LO feedthrough can be nulled by applying the correct
dc offset voltages at the DAC output. This can be done either by
using the auxiliary DACs (Register 0x32, Register 0x33,
Register 0x36, and Register 0x37) or by using the digital dc
offset adjustments (Register 0x2C to Register 0x2F). Using the
auxiliary DACs has the advantage that none of the main DAC
dynamic range is used for performing the dc offset adjustment.
The disadvantage is that the common-mode level of the output
signal changes as a function of the auxiliary DAC current. The
opposite is true when the digital offset adjustment is used.
Rev. PrA | Page 62 of 73
Good sideband suppression requires both gain and phase matching
of the I and Q signals. The phase adjust (Register 0x28 to
Register 0x2B) and gain control (Register 0x50 and Register 0x51)
registers can be used to calibrate I and Q transmit paths to optimize
the sideband suppression. As an alternative to the digital gain
scaling, the DAC full-scale output current (Register 0x30,
Register 0x31, Register 0x34, and Register 0x35) can also be
adjusted to calibrate the I and Q transmit paths; however, changing
the DAC full-scale output current affects the common-mode
voltage level.
For more information on correcting imperfections in IQ
modulators to improve RF signal fidelity, refer to Application
Note AN-1039.
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