AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 26

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AD9148BPCZ

Manufacturer Part Number
AD9148BPCZ
Description
Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
Manufacturer
AD [Analog Devices]
Datasheet
AD9148
Register Name
Data Format
Interrupt Enable 0
Interrupt Enable 1
Addr
(Hex)
03
04
05
Bit
7
6
5
4
3
2
7
6
5
4
2
1
0
4
3
2
Name
Binary format
Q first enable
Dual port mode
Bus swap
Byte mode
Byte swap
Enable PLL lock lost
Enable PLL lock
Enable sync
lock lost
Enable sync lock
Enable FIFO
SPI aligned
Enable FIFO
Warning 1
Enable FIFO
Warning 2
Enable AED
compare pass
Enable AED
compare fail
Enable SED
compare fail
Rev. PrA | Page 26 of 73
0 = normal data input bus pin out (MSB to LSB).
Function
Input data is in twos complement format (0) or unsigned
binary format (1).
Indicates I/Q data pairing on data input; I first (0), Q first (1).
Number of input data ports used.
Single port (0), dual port (1).
0 = normal data input bus pin out (MSB to LSB).
1 = inverted data input bus pin out (LSB to MSB).
0 = data input bus is 16-bit wide on each port.
1 = data input bus is two 8-bit wide buses on Port A.
1 = inverted data input bus pin out (LSB to MSB).
Enables interrupt for PLL lock lost.
Enables interrupt for PLL lock.
Enables interrupt for sync lock lost.
Enables interrupt for sync lock.
Enables interrupt for FIFO SPI aligned.
Enables interrupt for FIFO Warning 1.
Enables interrupt for FIFO Warning 2.
Enable interrupt for AED compare pass.
Enables interrupt for AED compare fail.
Enables interrupt for SED compare fail.
Preliminary Technical Data
Default
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0

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