AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 40

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
BYTE MODE
In byte mode, a FRAME signal must be provided along with the
DCI signal and the data. The most significant byte of the data
should correspond with DCI being high, and the least significant
byte of the data should correspond with DCI being low. The
FRAME signal indicates to which DAC the data is intended.
When FRAME is high, data on the top half of the port (A[15:8])
is sent to DAC 1 and data on the bottom half of the port (A[7:0]) is
sent to DAC 3. When the FRAME is low, data on the top half of
the port is sent to DAC 2 and data on the bottom half of the
port is sent to DAC 4. This pattern continuously repeats as
shown in Figure 48.
FRAMEA
A[15:8]
A[7:0]
DCIA
DAC1H
DAC3H
Figure 48. Timing Diagram for Byte Mode
DAC1L
DAC3L
DAC2H
DAC4H
DAC2L DAC1H
DAC4L
DAC3H
DAC1L
DAC3L
DAC2H
DAC4H
DAC2L
DAC4L
Rev. PrA | Page 40 of 73
The AD9148 also includes a byte swap feature. By default, the
bytes should be formatted as MSB sent to Bit 15 on Bus 1 and
Bit 7 on Bus 2. When byte swap is enabled (Register 0x03[2]),
MSB should be sent to Bit 8 on Bus 1 and Bit 0 on Bus 2. This is
described in Table 14.
Table 14. Byte Swap Formatting
Byte Swap
0
0
1
1
DATA INTERFACE OPTIONS
To enable optimization of the data interface, some additional
options have been provided in the following registers:
•
•
•
Depending on the data rate and DCI vs. data skew, the internal
DCI can be inverted to make the valid data timing window.
Data format (Register 0x03)
Data receiver control (Register 0x14)
Data receiver status (Register 0x15)
Byte
MSB
LSB
MSB
LSB
Preliminary Technical Data
Data Set 1[15:8]
Data Set 1[8:15]
A[15:8]
Data Set 1[7:0]
Data Set 1[0:7]
A[7:0]
Data Set 2[15:8]
Data Set 2[7:0]
Data Set 2[8:15]
Data Set 2[0:7]