AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 46

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock to CLK, a
separate SYNC input signal is required for synchronization. To
synchronize devices, the CLK signals and the SYNC signals
must be distributed with low skew to all of the devices being
synchronized. This configuration is shown below in Figure 54.
Data Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in data rate mode. The procedure assumes that
the CLK and SYNC signals are applied to all of the devices.
Each individual device must follow the procedure.
The procedure for data rate synchronization when directly
sourcing the DAC sampling clock follows:
1.
2.
3.
Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
Reset the FIFO by strobing the FRAME signal for at least the
time interval needed to load complete data to the four DACs
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure, and at this
stage, all devices should be synchronized.
SAMPLE RATE CLOCK
SYNC CLOCK
FPGA
Figure 54. Typical Circuit Diagram for Synchronizing Devices to a System Clock
CLOCK DRIVER
CLOCK DRIVER
LOW SKEW
LOW SKEW
LENGTH TRACES
MATCHED
LENGTH TRACES
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MATCHED
To ensure that each of the DACs are updated with the correct
data on the same DACCLK edge, two timing relationships must
be met on each DAC. DCI (and data) must meet the setup and
hold times with respect to the rising edge of CLK, and REFCLK/
SYNC must also meet the setup and hold time with respect to
the rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dual-
port mode and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within t
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 55.
FRAME(2)
Figure 55. Synchronization Signal Timing Requirements in Data Rate Mode,
SYNC(2)
CLK(2)
CLK(1)
DCI(2)
t
SU_DCI
CLK
REFCLK/SYNC
FRAME
DCI
CLK
REFCLK/SYNC
FRAME
DCI
t
SKEW
t
H_DCI
SKEW
Preliminary Technical Data
+ t
OUTDLY
2× Interpolation
nanoseconds of each other. A
t
SU_SYNC
OUT1
OUT2
t
H_SYNC