AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 48

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
Timing Optimization
The SYNC signal is sampled by a version of the DACCLK. If
sampling errors are detected, the opposite sampling edge can be
selected to improve the sampling point. The sampling edge can be
selected by setting Bit 3, Register 0x10 (1 = rising and 0 = falling).
The synchronization logic resynchronizes when a phase change
between the SYNC signal and the state of the clock generation
state machine exceeds a threshold. To mitigate the effects of
Rev. PrA | Page 48 of 73
jitter and prevent erroneous resynchronizations, the relative
phase can be averaged. The amount of averaging is set by the
Sync Averaging[2:0] bits (Bits[2:0], Register 0x10) and can be
set from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as
large as possible while still meeting the allotted resynchronization
time interval.
Preliminary Technical Data