DAC1008D750HN NXP [NXP Semiconductors], DAC1008D750HN Datasheet - Page 39

• Manufacturer Part Number: DAC1008D750HN
• Manufacturer: NXP [NXP Semiconductors]

Table 17.
Address Register name
0
1
2
3
4
5
6
7
8
9
10 0Ah DAC_A_CFG_2
11 0Bh DAC_A_CFG_3
12 0Ch DAC_B_CFG_1
13 0Dh DAC_B_CFG_2
14 0Eh DAC_B_CFG_3
15 0Fh DAC_CFG
17 11h DAC_CURRENT_0 R/W
18 12h DAC_CURRENT_1 R/W
19 13h DAC_CURRENT_2 R/W
20 14h DAC_CURRENT_3 R/W
21 15h DAC_SEL_PH_
22 16h PHASECORR_
23 17h PHASECORR_
26 1Ah DAC_A_AUX_MSB R/W
27 1Bh DAC_A_AUX_LSB R/W
00h COMMON
01h TXCFG
02h PLLCFG
03h FREQNCO_LSB
04h FREQNCO_LISB
05h FREQNCO_UISB
06h FREQNCO_MSB
07h PHINCO_LSB
08h PHINCO_MSB
09h DAC_A_CFG_1
FINE
CNTRL0
CNTRL1
10.15.2.1 Page 0 allocation map description
Page 0 register allocation map
R/W Bit definition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W PHASE_CORR_
b7
DAC_A_PD
DAC_B_PD
AUX_A_PD
DAC_A_GAIN_COARSE[1:0]
DAC_A_GAIN_COARSE[3:2]
DAC_B_GAIN_COARSE[1:0]
DAC_B_GAIN_COARSE[3:2]
NCO_EN
ENABLE
SPI_3W
PLL_PD
-
-
-
DAC_DRV_BIAS[2:0]
DAC_CK_BIAS[2:0]
b6
DAC_A_SLEEP
DAC_B_SLEEP
NCO_LP_SEL
SPI_RST
-
-
-
-
-
-
b5
INV_SINE_EN
-
-
-
-
-
-
-
PHASE_CORR[7:0]
FREQ_NCO[23:16]
FREQ_NCO[31:24]
FREQ_NCO[15:8]
FREQ_NCO[7:0]
PH_NCO[15:8]
PH_NCO[7:0]
AUX_A[9:2]
b4 b3
-
-
-
-
-
-
-
-
-
PLL_DIV[1:0]
MODE[2:0]
DAC_A_GAIN_FINE[5:0]
DAC_B_GAIN_FINE[5:0]
DAC_A_OFFSET[11:6]
DAC_B_OFFSET[11:6]
DAC_A_OFFSET[5:0]
DAC_B_OFFSET[5:0]
DAC_MST_BIAS[2:0]
DAC_CAS_BIAS[2:0]
DAC_DIG_BIAS[2:0]
DAC_SLV_BIAS[2:0]
-
-
-
-
-
b2
PLL_PHASE[1:0]
DF
-
-
-
-
b1
PD_ALL
MINUS_
3DB
PHASE_CORR[9:8]
SEL_PH_FINE[1:0]
INT_FIR[1:0]
AUX_A[1:0]
b0
PLL_POL
SHAPER
PD_GAP
NOISE_
-
-
-
-
Default
Bin
10000100 84h
00000001 01h
00000000 00h
01100110 66h
01100110 66h
01100110 66h
00100110 26h
00000000 00h
00000000 00h
00000000 00h
01000000 40h
11000000 C0h
00000000 00h
01000000 40h
11000000 C0h
00000000 00h
00000110 06h
00000110 06h
01100110 66h
01100110 66h
00000010 02h
00000000 00h
00000000 00h
10000000 80h
00000000 00h
Hex