DAC1008D750HN NXP [NXP Semiconductors], DAC1008D750HN Datasheet - Page 26

• Manufacturer Part Number: DAC1008D750HN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1008D750
Product data sheet
10.4 Clock input
The DAC1008D750 has one differential clock input, CLKINN/CLKINP.
The DAC1008D750 can operate with a clock frequency up to 312.5 MHz or up to 750 MHz
if the internal PLL is bypassed. The clock input can be LVDS (see
also be interfaced with CML (see
clock domain to another one is handled by Clock Domain Interface (CDI) logic.
During the reset phase (RESET_N asserted), the clock must be stable and running. This
ensures a proper reset of the complete device.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
Fig 15. LVDS clock configuration
Fig 16. Interfacing CML to LVDS
All information provided in this document is subject to legal disclaimers.
CML
Rev. 2 — 5 January 2011
Z
LVDS
diff = 100 Ω
Z
Figure
diff
= 100 Ω
1 kΩ
100 nF
100 nF
2×, 4× or 8× interpolating DAC with JESD204A
16). Error free data transition from one internal
V
DDA(1V8)
AGND
CLKINP
CLKINN
100 Ω
1.1 kΩ
2.2 kΩ
55 Ω
55 Ω
CLKINN
CLKINP
100 nF
001aah021
DAC1008D750
LVDS
Figure
001aah020
LVDS
© NXP B.V. 2011. All rights reserved.
15) but it can
26 of 99