DAC1008D750HN NXP [NXP Semiconductors], DAC1008D750HN Datasheet - Page 11

• Manufacturer Part Number: DAC1008D750HN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 5.
V
+85
maximum sample rate; PLL off unless otherwise specified.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
DAC1008D750
Product data sheet
Symbol
ACPR
NSD
DDA(1V8)
°
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It
reflects the delay required by DAC1008D750 to lock to a JESD204A stream. It supposes that the TX is already transmitting
K28.5 characters in error-free conditions.
CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see
Figure
|V
and the inductance between the receiver and the driver circuit ground voltage.
Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to V
SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 Ω
and 120 Ω.
Optimum performances at high sampling rate (> 650 Msps) will be achieved with V
IMD3 rejection with −6 dBFS/tone.
C; typical values measured at V
gpd
| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
= V
15) should be connected across the pins.
Characteristics
DDD
Parameter
adjacent channel
power ratio
noise spectral density
= 1.7 V to 1.9 V; V
…continued
DDA(3V3)
DDA(1V8)
Conditions
NCO on; 4× interpolation;
f
MHz
1 carrier; BW = 5 MHz
2 carriers; BW = 10 MHz
4 carriers; BW = 20 MHz
NCO on; 4× interpolation;
f
MHz
1 carrier; BW = 5 MHz
2 carriers; BW = 10 MHz
4 carriers; BW = 20 MHz
f
4× interpolation;
f
s
s
s
o
All information provided in this document is subject to legal disclaimers.
= 737.28 Msps; f
= 737.28 Msps; f
= 737.28 Msps;
= 153.6 MHz at 0 dBFS
= 3.13 V to 3.47 V; AGND and GND are shorted together; T
= V
DDD
Rev. 2 — 5 January 2011
= 1.8 V; V
o
o
= 96
= 153.6
DDA(3V3)
2×, 4× or 8× interpolating DAC with JESD204A
= 3.3 V; T
Test
C
C
C
C
C
C
I
[1]
DDA(1V8)
tt
[7]
[7]
[7]
amb
via 50 Ω (see
Min
-
-
-
-
-
-
-
= +25
= 1.8 V ± 2 %
DAC1008D750
°
C; R
Typ
67
64
60
67
64
59
−145
Figure
L
= 50
4).
-
-
-
-
-
-
Max
-
Ω
amb
© NXP B.V. 2011. All rights reserved.
; I
O(fs)
=
−
40
= 20 mA;
°
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBm/Hz
C to
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