PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 23
PCA9665D
Manufacturer Part Number
PCA9665D
Description
Fm+ parallel bus to I2C-bus controller
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCA9665D.pdf
(90 pages)
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NXP Semiconductors
PCA9665_3
Product data sheet
Fig 8.
successful
reception from
a Slave Transmitter
next transfer started with a
repeated START condition
Not Acknowledge received after
the slave address
arbitration lost in slave address
or Acknowledge bit
arbitration lost and addressed as slave
(1) See
(2) Defined state when a single byte is received and an ACK is sent (AA = 1).
(3) Defined state when a single byte is received and a NACK is sent (AA = 0).
(4) Master Transmitter Byte mode is entered when MODE = 0. Master Transmitter Buffered mode is entered when MODE = 1.
Format and states in the Master Receiver Byte mode (MODE = 0)
DATA
Table
from master to slave
from slave to master
28.
08h
A
S
n
any number of data bytes and
their associated Acknowledge bits
This number (contained in I2CSTA) corresponds
to a defined state of the I
SLA
R
MR
A or A
B0h
D8h
40h
48h
38h
68h
2
A
A
A
C-bus.
Rev. 03 — 12 August 2008
(1)
other MST
continues
other MST
continues
F8h
P
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
to corresponding states in Slave Receiver mode (General Call)
DATA
50h
(2)
A
Fm+ parallel bus to I
DATA
58h
38h
A
(3)
A
F8h
10h
other MST
continues
to Master Transmitter mode
P
S
PCA9665
© NXP B.V. 2008. All rights reserved.
2
SLA
C-bus controller
entry = MT
002aab025
W
R
(4)
23 of 90
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