PCA9541PW/03 NXP [NXP Semiconductors], PCA9541PW/03 Datasheet - Page 7

• Manufacturer Part Number: PCA9541PW/03
• Description: 2-to-1 I2C-bus master selector with interrupt logic and reset
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
8. Functional description
PCA9541_5
Product data sheet
8.1 Device address
8.2 Command Code
Refer to
Following a START condition, the upstream master that wants to control the I
make a status check must send the address of the slave it is accessing. The slave
address of the PCA9541 is shown in
resistors are incorporated on the hardware selectable pins and they must be pulled HIGH
or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while logic 0 selects a write operation.
Remark: Reserved I
with:
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9541, which will be stored in the Command Code register.
The 2 LSBs are used as a pointer to determine which register will be accessed.
If the auto-increment flag is set (AI = 1), the two least significant bits of the Command
Code are automatically incremented after a byte has been read or written. This allows the
user to program the registers sequentially or to read them sequentially.
Fig 5. Slave address
Fig 6. Command Code
•
•
•
‘reserved for future use’ I
slave devices that use the 10-bit addressing scheme (1111 0XX)
During a read operation, the contents of these bits will roll over to ‘00’ after the last
allowed register is accessed (‘10’).
Figure 1 “Block diagram of
2
C-bus addresses must be used with caution since they can interfere
Rev. 05 — 1 October 2007
2-to-1 I
2
C-bus addresses (1111 1XX)
0
1
2
fixed
0
C-bus master selector with interrupt logic and reset
1
PCA9541”.
auto-increment
Figure
0
1
AI
A3
5. To conserve power, no internal pull-up
selectable
hardware
0
A2
0
A1
register number
B1
002aab391
A0 R/W
002aab390
B0
PCA9541
© NXP B.V. 2007. All rights reserved.
2
C-bus or
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