PCA9541PW/03 NXP [NXP Semiconductors], PCA9541PW/03 Datasheet - Page 17

• Manufacturer Part Number: PCA9541PW/03
• Description: 2-to-1 I2C-bus master selector with interrupt logic and reset
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 14.
Legend: * default value
[1]
[2]
[3]
[4]
[5]
PCA9541_5
Product data sheet
Bit
2
1
0
Default values are the same for PCA9541/01, PCA9541/02, and PCA9541/03.
Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:
INT_IN lines goes HIGH for INTIN bit
TESTON bit is cleared for MYTEST bit
NTESTON bit is cleared for NMYTEST bit
Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.
BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the
register gets cleared on the second clock pulse during the read operation.
If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been
masked).
Symbol
BUSOK
BUSINIT
INTIN
Register 2 - Interrupt Status (ISTAT) register bit description
[2]
[4]
[4]
8.5 Power-on reset
When power is applied to V
condition until V
internal registers are initialized to their default states, with:
Access Value
R only
R only
R only
•
•
PCA9541/01: default Channel 0 (no STOP detect)
After power-up and/or insertion of the device in the main I
Channel 0 and the downstream slave channel are connected together.
PCA9541/02: default Channel 0 (STOP detect)
After power-up and/or insertion of the device in the main I
Channel 0 and the downstream slave channel are connected together after a STOP
condition has been detected by the PCA9541/02 on Channel 0.
– If the bus was not idle, Channel 0 and the downstream slave device will be
– If the bus was idle, then Channel 0 is connected to the downstream slave channel
– If a switch to Channel 1 (initiated by the master on Channel 1) is requested (before
connected together as soon as a STOP condition occurs at the conclusion of the
transmission sequence on Channel 0.
after a STOP condition is detected on Channel 0. This I
may not be addressed to the PCA9541/02.
or after the default switch to Channel 0 has been performed), the upstream
Channel 1 is connected to the downstream slave channel when the master located
in Channel 1 sends the STOP command.
0*
1
0*
1
0*
1
[1]
DD
Description
no interrupt generated by bus sensor function
interrupt generated by bus sensor function (masked when bus
recovery/initialization requested) - Bus was not idle when the switch occurred
no interrupt generated by the bus recovery/initialization function
interrupt generated by the bus recovery/initialization function;
recovery/initialization done
no interrupt on interrupt input (INT_IN)
interrupt on interrupt input (INT_IN)
has reached V
Rev. 05 — 1 October 2007
2-to-1 I
DD
, an internal power-on reset holds the PCA9541 in a reset
2
POR
C-bus master selector with interrupt logic and reset
. At this point, the reset condition is released and the
…continued
[5]
[5]
2
2
2
C-bus, the upstream
C-bus, the upstream
C-bus command may or
PCA9541
© NXP B.V. 2007. All rights reserved.
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