PCA9541PW/03 NXP [NXP Semiconductors], PCA9541PW/03 Datasheet - Page 33

• Manufacturer Part Number: PCA9541PW/03
• Description: 2-to-1 I2C-bus master selector with interrupt logic and reset
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
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[5]
[6]
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PCA9541_5
Product data sheet
Fig 23. Definition of timing on the I
Fig 24. I
C
Measurements taken with 1 k pull-up resistor and 50 pF load.
Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
Upon reset, the full delay will be the sum of t
b
SDA
SCL
= total capacitance of one bus line in pF.
Rise and fall times, refer to V
2
C-bus timing diagram
P
t
BUF
protocol
SDA
SCL
S
t
SU;STA
t
t
HD;STA
BUF
condition
t
LOW
START
(S)
t
HD;STA
IL
and V
2
C-bus
t
t
t
LOW
r
HD;DAT
t
r
IH
MSB
bit 7
(A7)
.
rst
t
and the RC time constant of the SDA bus.
HIGH
Rev. 05 — 1 October 2007
t
t
HIGH
SU;DAT
t
2-to-1 I
f
1
/f
bit 6
(A6)
SCL
t
f
t
2
HD;DAT
t
C-bus master selector with interrupt logic and reset
SU;DAT
(R/W)
bit 0
t
VD;DAT
acknowledge
Sr
(A)
t
SU;STA
t
HD;STA
t
VD;ACK
condition
STOP
(P)
t
SU;STO
002aab175
t
SP
t
SU;STO
PCA9541
© NXP B.V. 2007. All rights reserved.
002aaa986
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