PCA9541PW/03 NXP [NXP Semiconductors], PCA9541PW/03 Datasheet - Page 23
PCA9541PW/03
Manufacturer Part Number
PCA9541PW/03
Description
2-to-1 I2C-bus master selector with interrupt logic and reset
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.PCA9541PW03.pdf
(43 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9541PW/03
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested)
(1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x0101 was read (MASTER 1 controlling the bus).
SDA_MST0
SCL_MST0
INT1
SCL_SLAVE
SDA_SLAVE
INT0
S
START condition
1 1 1 A3 A2 A1 A0 0
slave address
(1)
acknowledge
from slave
R/W
A
MASTER 1 has control of the bus
0 0 0 AI 0 0 0 1
command code register
increment
auto
acknowledge
from slave
A
0 0 0 1 0 1 0 0
if the interrupt is not masked
data Control register
BUSINIT
(BUSLOSTMSK = 0)
BUSON
acknowledge
MYBUS
from slave
(between STOP and START) defined in the I
A
before sending commands to the downstream devices.
P
STOP
condition
MASTER 0 must wait for the 'bus free time' value
After the STOP condition
MASTER 1 is disconnected
from the downstream channel.
1 2 3 4 5 6 7 8 9
PCA9541 has control of the bus
if the interrupt is not masked
(BUSINITMSK = 0)
2
C-bus specification
STOP command
A
MASTER 0
has control
of the bus
002aab609