PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 50

• Manufacturer Part Number: PCF8523
• Description: Real-Time Clock (RTC) and calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
12. Dynamic characteristics
Table 47.
All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %
and 70 % with an input voltage swing of V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
PCF8523
Product data sheet
Symbol Parameter
Pin SCL
f
t
t
Pin SDA
t
t
Pins SCL and SDA
t
t
t
t
t
t
C
t
t
t
SCL
LOW
HIGH
SU;DAT
HD;DAT
BUF
SU;STO
HD;STA
SU;STA
r
f
VD;ACK
VD;DAT
SP
b
Fast mode plus guaranteed at 3.0 V < V
The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL
is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of the falling edge of SCL.
The maximum t
series protection resistors to be connected between the SDA pin, the SCL pin and the SDA/SCL bus lines without exceeding the
maximum t
t
t
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
VD;ACK
VD;DAT
SCL clock frequency
LOW period of the SCL clock -
HIGH period of the SCL clock -
data set-up time
data hold time
bus free time between a
STOP and START condition
set-up time for STOP
condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
rise time of both SDA and
SCL signals
fall time of both SDA and SCL
signals
capacitive load for each bus
line
data valid acknowledge time
data valid time
pulse width of spikes that
must be suppressed by the
input filter
= minimum time for valid SDA output following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA output LOW.
I
2
C-bus interface timing
f
.
f
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t
DD
Conditions Standard mode Fast mode (FM) Fast mode plus (Fm+)
[2]
-
-
-
-
-
-
[3][4]
[3][4]
[5]
[6]
[7]
SS
All information provided in this document is subject to legal disclaimers.
< 5.5 V.
to V
DD
Rev. 3 — 30 March 2011
(see
250
Min
-
4.7
4.0
0
4.7
4.0
4.0
4.7
-
-
-
-
-
-
Figure
34).
Max
100
-
-
-
-
-
-
-
-
1000
300
400
3.45
3.45
50
Min
-
1.3
0.6
100
0
1.3
0.6
0.6
0.6
20 + 0.1C
20 + 0.1C
-
-
-
-
Real-Time Clock (RTC) and calendar
b
b
Max Min
400 -
-
-
-
-
-
-
-
-
300 -
300 -
400 -
0.9
0.9
50
0.5
0.26
50
0
0.5
0.26
0.26
0.26
-
-
-
IL
of the SCL signal) in order to
f
is 250 ns. This allows
PCF8523
© NXP B.V. 2011. All rights reserved.
Max
1000
-
-
-
-
-
-
-
-
120
120
550
0.45
0.45
50
[1]
50 of 66
Unit
kHz
s
s
ns
ns
s
s
s
s
ns
ns
pF
s
s
ns