PCF8523 NXP [NXP Semiconductors], PCF8523 Datasheet - Page 25

no-image

PCF8523

Manufacturer Part Number
PCF8523
Description
Real-Time Clock (RTC) and calendar
Manufacturer
NXP [NXP Semiconductors]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8523T
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8523T/1
Manufacturer:
CDE
Quantity:
12 000
Part Number:
PCF8523T/1
Manufacturer:
NXP
Quantity:
9 029
Part Number:
PCF8523T/1
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8523T/1
0
Part Number:
PCF8523T/1,118
Manufacturer:
NXP
Quantity:
3 188
Part Number:
PCF8523T/1.118
0
Part Number:
PCF8523TK/1,118
Manufacturer:
MOLEX
Quantity:
10 000
Part Number:
PCF8523TS/1
Manufacturer:
VISHAY
Quantity:
6 758
Part Number:
PCF8523TS/1
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8523TS/1
0
Part Number:
PCF8523TS/1,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
PCF8523
Product data sheet
When one or several alarm registers are loaded with a valid minute, hour, day, or weekday
value and its corresponding alarm enable bit (AE_x) is logic 0, then that information is
compared with the current minute, hour, day, and weekday value. When all enabled
comparisons first match, the alarm flag, AF (register Control_2), is set logic 1.
The generation of interrupts from the alarm function is controlled via bit AIE (register
Control_1). If bit AIE is enabled, then the INT1 pin follows the condition of bit AF. AF will
remain set until cleared by the interface. Once AF has been cleared, it will only be set
again when the time increments to match the alarm condition once more. Alarm registers,
which have their AE_x bit logic 1 are ignored. The generation of interrupts from the alarm
function is described more detailed in
Table 24
write command, therefore bits 2, 1, and 0 must be re-written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed
during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by
writing logic 1. Writing logic 1 will result in the flag value remaining unchanged.
Table 24.
Table 25
CTBG, and bit SF are unaffected.
Table 25.
[1]
Register
Control_2
Register
Control_2
Fig 16. Alarm flag timing
The bits labelled as - have to be rewritten with the previous values.
and
shows what instruction must be sent to clear bit AF. In this example, bit CTAF,
Example where only the minute alarm is used and no other interrupts are enabled.
Flag location in register Control_2
Example to clear only AF (bit 3)
Table 25
Bit
7
WTAF
Bit
7
0
All information provided in this document is subject to legal disclaimers.
INT when AIE = 1
minutes counter
minute alarm
show an example for clearing bit AF. Clearing the flag is made by a
Rev. 3 — 30 March 2011
6
CTAF
6
1
AF
44
45
5
CTBF
5
1
Section
[1]
4
SF
4
1
8.4.
Real-Time Clock (RTC) and calendar
45
3
AF
3
0
2
-
2
-
001aaf903
46
PCF8523
© NXP B.V. 2011. All rights reserved.
1
-
1
-
0
-
0
-
25 of 66

Related parts for PCF8523