CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 8

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty flag to reflect the new level of fill. Therefore, the
Almost empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time t
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of the FIFO is synchronized to port A
clock. The state machine that controls an Almost Full flag
monitors a write pointer and read pointer comparator that
indicates when the FIFO SRAM status is almost full, or almost
full–1. The Almost Full state is defined by the contents of
register Y for AF. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Full flag is LOW
when the number of words in its FIFO is greater than or equal
to (1024–Y), (4096–Y), or (16384–Y) for the CY7C436x3
respectively. An Almost Full flag is HIGH when the number of
words in its FIFO is less than or equal to [1024–(Y+1)],
[4096–(Y+1)], or [16384–(Y+1)], for the CY7C436x3 respec-
tively.
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [1024/4096/16384–(Y+1)]. An Almost Full
flag is set HIGH by the second LOW-to-HIGH transition of its
synchronizing clock after the FIFO read that reduces the
number of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins the first synchronization cycle if it occurs at time
t
words in memory to [1024/4096/16384–(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first
synchronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable width of both the Mail1 and Mail2
registers matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A
Mail1 Register when a Port A write is selected by CSA, W/RA,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bits, then the usable width of the Mail1 Register
employs data lines A
bits, then the usable width of the Mail1 Register employs data
lines A
selected Port A bus size is 9 bits, then the usable width of the
SKEW2
[2]
0-17
or greater after the read that reduces the number of
. (In this case, A
0–35
. If the selected Port A bus size is 18
18–35
are “don’t care” inputs.) If the
0-35
data to the
SKEW2
or
Mail1 Register employs data lines A
“don’t care” inputs.)
A LOW-to-HIGH transition on CLKB writes B
Mail2 register when a Port B write is selected by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
also 36 bits, then the usable width of the Mail2 Register
employs data lines B
bits, then the usable width of the Mail2 register employs data
lines B
selected Port B bus size is 9 bits, then the usable width of the
Mail2 Register employs data lines B
“don’t care” inputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B read is
selected by CSB, W/RB, and ENB with MBB HIGH. For a
36-bit bus size, 36 bits of mailbox data are placed on B
For an 18-bit bus size, 18 bits of mailbox data are placed on
B
size, 9 bits of mailbox data are placed on B
B
The Mail2 Register flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A read is
selected by CSA, W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A
placed on A
a 9-bit bus size, 9 bits of mailbox data are placed on A
this case, A
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizing
The Port B bus can be configured in a 36-bit long-word, 18-bit
word, or 9-bit byte format for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Select (BM) determine the Port B bus size. These levels
should be static throughout FIFO operation. Both bus size
selections are implemented at the completion of Master Reset,
by the time the Full/Input Ready flag is set HIGH.
Two different methods for sequencing data transfer are
available for Port B when the bus size selection is either
byte-or word-size. They are referred to as Big Endian (most
significant byte first) and Little Endian (least significant byte
first). The level applied to the Big Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1/MRS2 selects the
endian method that will be active during FIFO operation. BE is
a don’t care input when the bus size selected for Port B is
long-word. The endian method is implemented at the
completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH.
Only 36-bit long-word data is written to or read from the two
FIFO memories on the CY7C436x3. Bus-matching operations
are done after data is read from the FIFO. These bus-matching
0–17
9–35
0–35
. (In this case, B
. For an 18-bit bus size, 18 bits of mailbox data are
are indeterminate.)
0–17
. (In this case, B
9–35
0–17
. (In this case, A
are indeterminate.)
0–35
18–35
. If the selected Port B bus size is 18
18–35
are indeterminate.) For a 9-bit bus
are “don’t care” inputs.) If the
18–35
0–8
0-8
. (In this case, A
. (In this case, B
are indeterminate.) For
CY7C43643
CY7C43663
CY7C43683
0–8
0-35
. (In this case,
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data to the
9–35
9-35
0–8
0–35
. (In
are
are
.