CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 17

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
Switching Waveforms
Notes:
22. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
23. t
24. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
25. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
Parallel Programming of the Almost Full Flag and Almost Empty Flag Offset Values after Reset
FF/IR
(CY Standard and FWFT Modes)
SPM
FS1/SEN
Serial Programming of the Almost Full Flag and Almost Empty Flag
Offset Values (CY Standard and FWFT Modes)
CLKA
MRS1, MRS2
FS0/SD
CLKA
MRS1,
MRS2
SPM
FS1/SEN,
FS0/SD
FF/IR
ENA
A
0 35
of CLKA and rising edge of CLKB is less than t
SKEW1
[25]
is the minimum time between the rising CLKA edge and a rising CLKB for FF/IR to transition HIGH in the next cycle. If the time between the rising edge
t
FSS
t
t
FSS
FSS
t
FSS
t
t
FSH
FSH
t
FSH
t
(continued)
SPH
[22]
t
AF Offset (Y) MSB
SDS
SKEW1
t
SENS
, then FF/IR may transition HIGH one cycle later than shown.
t
WFF
t
SENH
AF Offset (Y)
[24]
t
SDH
t
DS
t
DH
t
SENS
AE Offset (X)
t
t
AE Offset (X) LSB
ENS
SDS
t
ENH
t
t
SDH
SENH
First Word to FIFO
t
WFF
t
SKEW1
CY7C43643
CY7C43663
CY7C43683
[23]
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