CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 26

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
Switching Waveforms
Notes:
46. If Port B is configured for word size, data can be written to the Mail2 register using B
47. Retransmit is performed in the same manner for FIFO2.
48. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of RT1, and
49. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
50. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after t
51. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
EFB/FFA
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
CLKB
CSB
W/RB
MBB
ENB
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
B
0 35
0–35
CLKA
CLKB
data (A
this second case, A
during the retransmit operation, i.e. when RT1 is LOW and t
the Retransmit setup.
FIFO1 Retransmit Timing
ENB
RT1
[27]
[44]
18–35
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B
0–8
will have valid data (A
(continued)
t
EN
[47, 48, 49, 50, 51]
t
RSTS
FIFO2 Output Register
9–35
t
t
t
ENS
t
ENS
ENS
ENS
t
W1
DS
will be indeterminate).
t
t
t
t
ENH
t
DH
ENH
ENH
ENH
t
MDV
RTR
t
PMF
after the RT1 rising edge.
t
PMR
RTR
to update these flags.
0–17
(B
W1 (Remains valid in Mail2 Register after read)
18–35
are “don’t care” inputs). In this first case, A
[46,45]
t
ENS
t
RSTH
t
ENH
t
PMF
0–8
t
RTR
(B
9–35
are “don’t care” inputs). In
CY7C43643
CY7C43663
CY7C43683
t
DIS
0–17
Page 26 of 29
RTR
will have valid
.