CY7C43643 CYPRESS [Cypress Semiconductor], CY7C43643 Datasheet - Page 14

• Manufacturer Part Number: CY7C43643
• Description: 1K/4K/16K x36 Unidirectional Synchronous FIFO with Bus Matching
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06021 Rev. *B
AC Test Loads and Waveforms (-7)
Switching Characteristics
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
17. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Parameter
S
CLK
CLKH
CLKL
DS
ENS
RSTS
FSS
BES
SPMS
SDS
SENS
FWS
DH
ENH
RSTH
FSH
BEH
SPMH
SDH
SENH
SPH
I/O
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
Set-up Time, A
before CLKB
Set-up Time, CSA, W/RA, ENA, and MBA before
CLKA ; CSB, W/RB, ENB, and MBB before
CLKB
Set-up Time, MRS1/MRS2, PRS or RT1 LOW
before CLKA or CLKB
Set-up Time, FS0 and FS1 before MRS1/MRS2
HIGH
Set-up Time, BE/FWFT before MRS1/MRS2 HIGH
Set-up Time, SPM before MRS1/MRS2 HIGH
Set-up Time, FS0/SD before CLKA
Set-up Time, FS1/SEN before CLKA
Set-up Time, FWFT before CLKA
Hold Time, A
CLKB
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA ; CSB, W/RB, ENB, and MBB after CLKB
Hold Time, MRS1/MRS2, PRS or RT1 LOW after
CLKA or CLKB
Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH
Hold Time, BE/FWFT after MRS1/MRS2 HIGH
Hold Time, SPM after MRS1/MRS2 HIGH
Hold Time, FS0/SD after CLKA
Hold Time, FS1/SEN after CLKA
Hold Time, FS1/SEN HIGH after MRS1/MRS2
HIGH
Z0 = 50
0–35
0–35
after CLKA and B
[17]
Description
before CLKA and B
Over the Operating Range
50
[17]
V
CC
/2
0–35
0–35
after
GND
3.0V
Min.
CY7C43643/
7.5
3.5
3.5
2.5
3
3
6
5
5
3
3
0
0
0
1
1
1
1
0
0
0
63/83
–7
3 ns
Max.
133
ALL INPUT PULSES
10%
90%
Min.
CY7C43643/
10
4
4
4
4
4
7
7
7
4
4
0
0
0
2
1
1
1
0
0
1
63/83
–10
Max.
100
90%
Min.
CY7C43643/
10%
7.5
7.5
7.5
15
6
6
5
5
5
5
5
0
0
0
4
2
2
2
0
0
2
CY7C43643
CY7C43663
CY7C43683
63/83
–15
3 ns
Page 14 of 29
Max.
67
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns