CY7C1471V33_12 CYPRESS [Cypress Semiconductor], CY7C1471V33_12 Datasheet - Page 6

• Manufacturer Part Number: CY7C1471V33_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Functional Overview
The CY7C1471V33 is synchronous flow through burst SRAMs
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (t
(133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). Byte write select (BW
byte write operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
■
■
■
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is be tri-stated immediately.
Burst Read Accesses
The CY7C1471V33 have an on-chip burst counter that enables
the user to supply a single address and conduct up to four reads
without reasserting the address inputs. ADV/LD must be driven
LOW to load a new address into the SRAM, as described in the
Single Read Accesses
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
Document Number: 38-05288 Rev. *N
CEN is asserted LOW
CE
WE is deasserted HIGH
ADV/LD is asserted LOW.
1
, CE
1
, CE
2
, CE
2
, and CE
3
) active at the rising edge of the clock. If (CEN)
3
are all asserted active
section. The sequence of the burst
X
) can be used to conduct
1
, CE
2
, CE
CDV
3
) and an
) is 6.5 ns
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for Byte Write operations, see
Read/Write on page 9
and
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
signals. The CY7C1471V33 provides Byte Write capability that
is described in the
input WE with the selected BW
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self timed write
mechanism has been provided to simplify the write operations.
Byte
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1471V33 are common I/O devices, data must
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP
drivers. As a safety precaution, DQs and DQP
tri-stated during the data portion of a write cycle, regardless of
the state of OE.
Burst Write Accesses
The CY7C1471V33 have an on-chip burst counter that enables
the user to supply a single address and conduct up to four write
operations without reasserting the address inputs. ADV/LD must
be driven LOW to load the initial address, as described in the
Single Write Accesses
the subsequent clock rise, the chip enables (CE
and WE inputs are ignored and the burst counter is incremented.
The correct BW
write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
write
the
3
3
, must remain inactive for the duration of t
are all asserted active, and (3) WE is asserted LOW.
write
capability
X
inputs must be driven in each cycle of the burst
Truth Table for Read/Write on page
for details) inputs is latched into the device
is
section. When ADV/LD is driven HIGH on
X
is
complete.
inputs. Doing so tri-states the output
included
X
input selectively writes to only
CY7C1471V33
Additional
to
X
greatly
are automatically
Truth Table for
1
, CE
ZZREC
Page 6 of 22
X
2
.
, and CE
accesses
after the
simplify
1
1
9. The
, CE
, CE
X
(or
3
2
2
X
)
,
,