CY7C1471V33_12 CYPRESS [Cypress Semiconductor], CY7C1471V33_12 Datasheet - Page 5

• Manufacturer Part Number: CY7C1471V33_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 38-05288 Rev. *N
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
DQ
DQP
MODE
V
V
V
NC
0
DD
DDQ
SS
, A
Name
1
2
3
s
A
C
, BW
, BW
X
1
, A
B
D
,
asynchronous
asynchronous
Input strap pin Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
Power supply Power supply inputs to the core of the device.
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
I/O power
Ground
supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
clock
I/O-
I/O-
I/O
–
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
A
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
edge of CLK.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
Advance/load input. Advances the on-chip address counter or loads a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded
into the device for an access. After being deselected, ADV/LD should must driven LOW to load a new
address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device is deselected.
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ
sequences, DQP
When tied to V
Power supply for the I/O circuitry.
Ground for the device.
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
[1:0]
are fed to the two-bit burst counter.
2
3
3
to select or deselect the device.
to select or deselect the device.
to select or deselect the device.
DD
X
or left floating selects interleaved burst sequence.
is controlled by BW
X
correspondingly.
Description
CY7C1471V33
s
. During write
s
Page 5 of 22
and DQP
X
2
1
1