CY7C1471V33_12 CYPRESS [Cypress Semiconductor], CY7C1471V33_12 Datasheet - Page 12

• Manufacturer Part Number: CY7C1471V33_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05288 Rev. *N
Parameter
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
14. Unless otherwise noted in the following table, timing reference level is 1.5 V when V
15. Test conditions shown in (a) of
16. This part has an internal voltage regulator; t
17. t
18. At any supplied voltage and temperature, t
19. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ALS
WES
CENS
DS
CES
AH
ALH
WEH
CENH
DH
CEH
be initiated.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z before low Z under the same system conditions.
CHZ
, t
CLZ
[16]
, t
[14, 15]
OELZ
, and t
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADV/LD setup before CLK rise
WE, BW
CEN setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADV/LD hold after CLK rise
WE, BW
CEN hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
OEHZ
are specified with AC test conditions shown in part (b)
Figure 2 on page 11
X
X
setup before CLK rise
hold after CLK rise
[17, 18, 19]
[17, 18, 19]
OEHZ
POWER
is less than t
is the time that the power needs to be supplied above V
unless otherwise noted.
[17, 18, 19]
[17, 18, 19]
OELZ
Description
and t
CHZ
is less than t
ofFigure 2 on page
DDQ
CLZ
= 3.3 V and is 1.25 V when V
to eliminate bus contention between SRAMs when sharing the same data
11. Transition is measured ±200 mV from steady-state voltage.
DD(minimum)
DDQ
initially, before a read or write operation can
= 2.5 V.
Min
7.5
2.5
2.5
2.5
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
0
–
CY7C1471V33
133 MHz
Max
6.5
3.8
3.0
3.0
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Unit
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