CY7C1470V25_11 CYPRESS [Cypress Semiconductor], CY7C1470V25_11 Datasheet - Page 9

• Manufacturer Part Number: CY7C1470V25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1470V25/CY7C1472V25/CY7C1474V25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
DQ
CY7C1472V25) inputs. Doing so will tri-state the output drivers.
As
(DQ
DQ
CY7C1472V25) are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an
on-chip burst counter that allows the user the ability to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the
Accesses
subsequent clock rise, the chip enables (CE
and WE inputs are ignored and the burst counter is incremented.
The correct BW (BW
CY7C1470V25 and BW
driven in each cycle of the burst write in order to write the correct
bytes of data.
ZZ Mode Electrical Characteristics
Document Number: 38-05290 Rev. *L
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b,c,d
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
Parameter
a
/DQP
/DQP
section above. When ADV/LD is driven HIGH on the
a,b,c,d
safety
a,b,c,d
/DQP
/DQP
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
for CY7C1470V25 and DQ
for CY7C1470V25 and DQ
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
a,b
precaution,
for CY7C1472V25) inputs must be
for CY7C1474V25, BW
Description
for
for
DQ
1
, CE
CY7C1474V25,
CY7C1474V25,
a,b
a,b
and
Single Write
2
/DQP
/DQP
, and CE
a,b,c,d
a,b
a,b
DQP
ZZ  V
ZZ V
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
for
for
for
3
)
DD
DD
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or V
 0.2 V
Test Conditions
 0.2 V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
11
3
00
01
10
11
, must remain inactive for the duration of t
Address
Second
Address
Second
A1, A0
A1, A0
01
00
11
10
01
10
00
11
2t
DD
Min
CYC
–
–
–
0
Address
)
Address
A1, A0
A1, A0
Third
Third
10
00
01
10
00
01
11
11
CY7C1470V25
CY7C1472V25
CY7C1474V25
2t
2t
Max
120
CYC
CYC
–
–
ZZREC
Address
Address
Fourth
Fourth
Page 9 of 31
A1, A0
A1, A0
Unit
mA
11
10
01
00
11
00
01
10
ns
ns
ns
ns
after the
1
, CE
2
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