CY7C1470V25_11 CYPRESS [Cypress Semiconductor], CY7C1470V25_11 Datasheet - Page 24

• Manufacturer Part Number: CY7C1470V25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 38-05290 Rev. *L
Switching Waveforms
NOP, STALL and DESELECT Cycles
ZZ Mode Timing
Notes
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in high Z when exiting ZZ sleep mode.
In-Out (DQ)
ADDRESS
ADV/LD
Data
BWx
CEN
CLK
WE
CE
ALL INPUTS
(except ZZ)
Outputs (Q)
WRITE
D(A1)
I
1
A1
SUPPLY
[28, 29]
1
CLK
ZZ
is LOW, CE
Q(A2)
READ
A2
2
2
is HIGH and CE
(continued)
t ZZI
STALL
t
I
ZZ
DDZZ
3
[25, 26, 27]
3
is LOW. When CE is HIGH,CE
D(A1)
Q(A3)
READ
A3
4
Q(A2)
WRITE
D(A4)
DON’T CARE
A4
DON’T CARE
5
High-Z
1
is HIGH or CE
STALL
6
Q(A3)
2
UNDEFINED
is LOW or CE
NOP
7
DESELECT or READ Only
t RZZI
Q(A5)
3
D(A4)
READ
t
ZZREC
A5
is HIGH.
8
DESELECT
CY7C1470V25
CY7C1472V25
CY7C1474V25
9
Page 24 of 31
CONTINUE
DESELECT
Q(A5)
10
t
CHZ
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